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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v3 017/162] tcg: Convert xor to TCGOutOpBinary
Date: Sun, 16 Feb 2025 15:07:46 -0800
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
tcg/tcg.c | 4 +++
tcg/aarch64/tcg-target.c.inc | 31 +++++++++++---------
tcg/arm/tcg-target.c.inc | 25 +++++++++++-----
tcg/i386/tcg-target.c.inc | 27 ++++++++++++-----
tcg/loongarch64/tcg-target.c.inc | 29 +++++++++++-------
tcg/mips/tcg-target.c.inc | 28 +++++++++++-------
tcg/ppc/tcg-target.c.inc | 30 +++++++++++--------
tcg/riscv/tcg-target.c.inc | 29 +++++++++++-------
tcg/s390x/tcg-target.c.inc | 50 ++++++++++++++++----------------
tcg/sparc64/tcg-target.c.inc | 23 +++++++++++----
tcg/tci/tcg-target.c.inc | 14 +++++++--
11 files changed, 186 insertions(+), 104 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index dc45df2869..d704ef8643 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1009,6 +1009,8 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
+ OUTOP(INDEX_op_xor_i32, TCGOutOpBinary, outop_xor),
+ OUTOP(INDEX_op_xor_i64, TCGOutOpBinary, outop_xor),
};
=20
#undef OUTOP
@@ -5434,6 +5436,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG=
Op *op)
case INDEX_op_andc:
case INDEX_op_or:
case INDEX_op_orc:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
{
const TCGOutOpBinary *out =3D
container_of(all_outop[op->opc], TCGOutOpBinary, base);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 13592303a8..d575635fe0 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2186,6 +2186,24 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_insn(s, 3510, EOR, type, a0, a1, a2);
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_logicali(s, I3404_EORI, type, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rL),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2267,17 +2285,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType ext,
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break;
=20
- case INDEX_op_xor_i32:
- a2 =3D (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_xor_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
- } else {
- tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
- }
- break;
-
case INDEX_op_eqv_i32:
a2 =3D (int32_t)a2;
/* FALLTHRU */
@@ -3023,8 +3030,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_mulsh_i64:
return C_O1_I2(r, r, r);
=20
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rL);
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 76d24e0440..00963d6f93 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1909,6 +1909,24 @@ static const TCGOutOpBinary outop_orc =3D {
.base.static_constraint =3D C_NotImplemented,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_dat_reg(s, COND_AL, ARITH_EOR, a0, a1, a2, SHIFT_IMM_LSL(0));
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_dat_imm(s, COND_AL, ARITH_EOR, a0, a1, encode_imm_nofail(a2));
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rI),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1971,10 +1989,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
args[0], args[1], args[2], const_args[2]);
}
break;
- case INDEX_op_xor_i32:
- c =3D ARITH_EOR;
- tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_arg=
s[2]);
- break;
case INDEX_op_add2_i32:
a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
a3 =3D args[3], a4 =3D args[4], a5 =3D args[5];
@@ -2232,9 +2246,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_muls2_i32:
return C_O2_I2(r, r, r, r);
=20
- case INDEX_op_xor_i32:
- return C_O1_I2(r, r, rI);
-
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index d278e61b85..928938509e 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2657,6 +2657,26 @@ static const TCGOutOpBinary outop_orc =3D {
.base.static_constraint =3D C_NotImplemented,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW;
+ tgen_arithr(s, ARITH_XOR + rexw, a0, a2);
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW;
+ tgen_arithi(s, ARITH_XOR + rexw, a0, a2, 0);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, 0, re),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2740,11 +2760,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
=20
OP_32_64(sub):
c =3D ARITH_SUB;
- goto gen_arith;
- OP_32_64(xor):
- c =3D ARITH_XOR;
- goto gen_arith;
- gen_arith:
if (const_a2) {
tgen_arithi(s, c + rexw, a0, a2, 0);
} else {
@@ -3666,8 +3681,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
return C_O1_I2(r, 0, re);
=20
case INDEX_op_shl_i32:
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.=
c.inc
index 9bfe1d6d6b..3775777db4 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1345,6 +1345,24 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_opc_xor(s, a0, a1, a2);
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_opc_xori(s, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rU),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1395,15 +1413,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- if (c2) {
- tcg_out_opc_xori(s, a0, a1, a2);
- } else {
- tcg_out_opc_xor(s, a0, a1, a2);
- }
- break;
-
case INDEX_op_extract_i32:
if (a2 =3D=3D 0 && args[3] <=3D 12) {
tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
@@ -2291,8 +2300,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
=20
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
/* LoongArch reg-imm bitops have their imms ZERO-extended */
return C_O1_I2(r, r, rU);
=20
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index f6987963ec..30fb01cb0a 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1734,6 +1734,24 @@ static const TCGOutOpBinary outop_orc =3D {
.base.static_constraint =3D C_NotImplemented,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rI),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1807,13 +1825,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
tcg_out_ldst(s, i1, a0, a1, a2);
break;
=20
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- i1 =3D OPC_XOR, i2 =3D OPC_XORI;
- if (c2) {
- tcg_out_opc_imm(s, i2, a0, a1, a2);
- break;
- }
do_binaryv:
tcg_out_opc_reg(s, i1, a0, a1, a2);
break;
@@ -2235,9 +2246,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_muls2_i64:
case INDEX_op_mulu2_i64:
return C_O2_I2(r, r, r, r);
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index ccd7812016..16d3dbd841 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2983,6 +2983,24 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out32(s, XOR | SAB(a1, a0, a2));
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_xori32(s, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rU),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -3068,15 +3086,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_xor_i64:
- case INDEX_op_xor_i32:
- a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
- if (const_args[2]) {
- tcg_out_xori32(s, a0, a1, a2);
- } else {
- tcg_out32(s, XOR | SAB(a1, a0, a2));
- }
- break;
case INDEX_op_eqv_i32:
if (const_args[2]) {
tcg_out_xori32(s, args[0], args[1], ~args[2]);
@@ -4141,7 +4150,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_st_i64:
return C_O0_I2(r, r);
=20
- case INDEX_op_xor_i32:
case INDEX_op_eqv_i32:
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@@ -4180,8 +4188,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
=20
case INDEX_op_sub_i32:
return C_O1_I2(r, rI, ri);
- case INDEX_op_xor_i64:
- return C_O1_I2(r, r, rU);
case INDEX_op_sub_i64:
return C_O1_I2(r, rI, rT);
case INDEX_op_clz_i32:
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 14216e9dff..c981ea389a 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2043,6 +2043,24 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rI),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2121,15 +2139,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
- }
- break;
-
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
if (c2) {
@@ -2695,8 +2704,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_st_i64:
return C_O0_I2(rz, r);
=20
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
case INDEX_op_negsetcond_i32:
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 97587939bd..bedad7137b 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2283,6 +2283,31 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ if (type !=3D TCG_TYPE_I32) {
+ tcg_out_insn(s, RRFa, XGRK, a0, a1, a2);
+ } else if (a0 =3D=3D a1) {
+ tcg_out_insn(s, RR, XR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRFa, XRK, a0, a1, a2);
+ }
+}
+
+static void tgen_xori_3(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_mov(s, type, a0, a1);
+ tgen_xori(s, a0, type =3D=3D TCG_TYPE_I32 ? (uint32_t)a2 : a2);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rK),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori_3,
+};
+
=20
# define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \
@@ -2351,18 +2376,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_xor_i32:
- a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tcg_out_insn(s, RIL, XILF, a0, a2);
- } else if (a0 =3D=3D a1) {
- tcg_out_insn(s, RR, XR, args[0], args[2]);
- } else {
- tcg_out_insn(s, RRFa, XRK, a0, a1, a2);
- }
- break;
-
case INDEX_op_eqv_i32:
a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2];
if (const_args[2]) {
@@ -2582,16 +2595,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_xor_i64:
- a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_xori(s, a0, a2);
- } else {
- tcg_out_insn(s, RRFa, XGRK, a0, a1, a2);
- }
- break;
-
case INDEX_op_eqv_i64:
a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
if (const_args[2]) {
@@ -3285,10 +3288,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsign=
ed flags)
=20
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- case INDEX_op_xor_i32:
return C_O1_I2(r, r, ri);
- case INDEX_op_xor_i64:
- return C_O1_I2(r, r, rK);
=20
case INDEX_op_eqv_i32:
return C_O1_I2(r, r, ri);
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 38b325e8a9..8a6c9852d2 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -1362,6 +1362,24 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_arith(s, a0, a1, a2, ARITH_XOR);
+}
+
+static void tgen_xori(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+ tcg_out_arithi(s, a0, a1, a2, ARITH_XOR);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, rJ),
+ .out_rrr =3D tgen_xor,
+ .out_rri =3D tgen_xori,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1419,9 +1437,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =
TCGType type,
OP_32_64(sub):
c =3D ARITH_SUB;
goto gen_arith;
- OP_32_64(xor):
- c =3D ARITH_XOR;
- goto gen_arith;
case INDEX_op_shl_i32:
c =3D SHIFT_SLL;
do_shift32:
@@ -1635,8 +1650,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_divu_i64:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shr_i32:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index b9309e2fb9..85caff300f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -101,8 +101,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned =
flags)
case INDEX_op_nand_i64:
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shr_i32:
@@ -686,6 +684,17 @@ static const TCGOutOpBinary outop_orc =3D {
.out_rrr =3D tgen_orc,
};
=20
+static void tgen_xor(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_op_rrr(s, glue(INDEX_op_xor_i,TCG_TARGET_REG_BITS), a0, a1, a2=
);
+}
+
+static const TCGOutOpBinary outop_xor =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_xor,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -730,7 +739,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TC=
GType type,
=20
CASE_32_64(sub)
CASE_32_64(mul)
- CASE_32_64(xor)
CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */
--=20
2.43.0