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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d5366729sm48960315ad.79.2025.02.15.16.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Feb 2025 16:01:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739664076; x=1740268876; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CPVDesfkRpmTOWA3zfnP41neg542OwOsuYWNBsm3NxY=; b=SZ3qzTDsNkdB1jAVe7FQu4wyR2oHv9JRJCaOFJ+5wot8JvLwEyV7R1z8hnOaXOsjeK GHTzs+BhrHLODktJXtMOUpP2XbNxnvoPjRNDMCLDDCvQ7qF6kuMYd2WY6813HwpXMgpk FE5sv2oDXPAQr8Utejf5myur6wrtcrJsRnMM9OsSKEssi6xmtrrCjeF+CaRU5qr/42Fz 9GKfzmiNvdkDT0/PjE+vyel7RJQ+CcmKZkwluEZ9IEDj2D2+G4QpXjNQmsZVKH2so/W+ VzTutfA+3S7PHTUuagB2mVQRDxhWzQyWsgZrt2+SBrF+BFDbW1DfS2G36GRGG8U4QoN1 Wd7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739664076; x=1740268876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CPVDesfkRpmTOWA3zfnP41neg542OwOsuYWNBsm3NxY=; b=lFRxGawooCPChXtnfXgLqUyrR9shrVrUVIQghkfafAlGRUjYMtXIv4fV8LwdDRCSbI SibFjNS1Cu858SPDlwH1rxMfp64VYlii2pQVtfogqet8Vb+L4QFnGw2PF8FHHLHciXct etksLeJfBeNnpBKfPUW6zkVBfs60AfuPIjiiFkq7DbLdwV9e7xlZMXdEzX9+MXkbuyfQ WVIEpfuhTRHXElD+u+cCsfm5dL8eoamh4XnGar88Rlquvli1HUqcvdGyxS1fm0SIJeWi XFWKChUe7wKlCEA7Fy9X9ZhVZNjXXfgmnWMCJ1inGrhAhYjaoRYbb1CUeURrhQUSOOJC erBA== X-Gm-Message-State: AOJu0YzwXB2SwcCbohtHm8M/YBEzp2C56EncuQFw6wE2pzdd0SdAoIno FLRNG3YgfaDHkB4D0q4NraHb3UGfMJbLgvIFXQQF2O/xhDPh7pIMcVQzmHWMefvxV+VIcJqlO46 T X-Gm-Gg: ASbGncskjL/rZZUa5L5visYiKvSupDcUqzpdm3OvrruwCFAfA3Ep2lV9i9ehuM8d1kZ 60X/DSO0QAWWvBSI5YrdzcTuLzDBJykY71v8mCFbHRx9UJHKLhUwSA6BHR89rMxA8RLmyBgKeOv X59a/fU/JEuXm0JVQ/V1AEcDT6hz2H0SPEUH7M+bDxC5FFcptnRrXZ8cn8+Qm5G2WIhL1+7iMOl 1H43k3FwGSvhoBSVjoAZELBsS3oR4dSTn7lPaOFKwwP6x2nuVpkbTjUctQ5KbAiUfYyKv9P/EDt lkXLadt7K14uPOebHRPT51C2RHhK53kZFZ2HvE9Wj9o1FFs= X-Google-Smtp-Source: AGHT+IHTuqlmeuyZ+VjZFKMG670lDEYsDDckPcB0z7MnXVXA4jh3FTV/o/SRWZ/gi6f6I2U9oTqQHg== X-Received: by 2002:a17:902:d58b:b0:220:c813:dfcb with SMTP id d9443c01a7336-2210408d75emr80085905ad.39.1739664076527; Sat, 15 Feb 2025 16:01:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 07/24] tcg/mips: Drop addrhi from prepare_host_addr Date: Sat, 15 Feb 2025 16:00:51 -0800 Message-ID: <20250216000109.2606518-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250216000109.2606518-1-richard.henderson@linaro.org> References: <20250216000109.2606518-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1739664400026019000 The guest address will now always fit in one register. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 62 ++++++++++++++------------------------- 1 file changed, 22 insertions(+), 40 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index b1d512ca2a..153ce1f3c3 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1217,8 +1217,7 @@ bool tcg_target_has_memory_bswap(MemOp memop) * is required and fill in @h with the host address for the fast path. */ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, - TCGReg addrlo, TCGReg addrhi, - MemOpIdx oi, bool is_ld) + TCGReg addr, MemOpIdx oi, bool = is_ld) { TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; @@ -1245,8 +1244,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; - ldst->addrlo_reg =3D addrlo; - ldst->addrhi_reg =3D addrhi; + ldst->addrlo_reg =3D addr; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); @@ -1254,11 +1252,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, =20 /* Extract the TLB index from the address into TMP3. */ if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); } else { - tcg_out_dsrl(s, TCG_TMP3, addrlo, - s->page_bits - CPU_TLB_ENTRY_BITS); + tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_B= ITS); } tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); =20 @@ -1288,48 +1285,35 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU), - TCG_TMP2, addrlo, s_mask - a_mask); + TCG_TMP2, addr, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); } else { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); } =20 /* Zero extend a 32-bit guest address for a 64-bit host. */ if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { - tcg_out_ext32u(s, TCG_TMP2, addrlo); - addrlo =3D TCG_TMP2; + tcg_out_ext32u(s, TCG_TMP2, addr); + addr =3D TCG_TMP2; } =20 ldst->label_ptr[0] =3D s->code_ptr; tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); =20 - /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { - /* delay slot */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); - - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); - - ldst->label_ptr[1] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); - } - /* delay slot */ base =3D TCG_TMP3; - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); } else { if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { ldst =3D new_ldst_label(s); =20 ldst->is_ld =3D is_ld; ldst->oi =3D oi; - ldst->addrlo_reg =3D addrlo; - ldst->addrhi_reg =3D addrhi; + ldst->addrlo_reg =3D addr; =20 /* We are expecting a_bits to max out at 7, much lower than AN= DI. */ tcg_debug_assert(a_bits < 16); - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); =20 ldst->label_ptr[0] =3D s->code_ptr; if (use_mips32r6_instructions) { @@ -1340,7 +1324,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } } =20 - base =3D addrlo; + base =3D addr; if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { tcg_out_ext32u(s, TCG_REG_A0, base); base =3D TCG_REG_A0; @@ -1460,14 +1444,13 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, } =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - MemOpIdx oi, TCGType data_type) + TCGReg addr, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); TCGLabelQemuLdst *ldst; HostAddress h; =20 - ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + ldst =3D prepare_host_addr(s, &h, addr, oi, true); =20 if (use_mips32r6_instructions || h.aa.align >=3D (opc & MO_SIZE)) { tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); @@ -1547,14 +1530,13 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - MemOpIdx oi, TCGType data_type) + TCGReg addr, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); TCGLabelQemuLdst *ldst; HostAddress h; =20 - ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + ldst =3D prepare_host_addr(s, &h, addr, oi, false); =20 if (use_mips32r6_instructions || h.aa.align >=3D (opc & MO_SIZE)) { tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); @@ -2096,24 +2078,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , TCGType type, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); + tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); + tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); } else { - tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); } break; =20 case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); + tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); + tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); } else { - tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); } break; =20 --=20 2.43.0