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[92.88.170.6]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aba532832dcsm121008166b.85.2025.02.13.04.22.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 13 Feb 2025 04:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739449380; x=1740054180; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r5LQvdlT1sMf3RQG3zaZimZ3xYwH68boESfP4z93+Xs=; b=MsQvugnhOZPJvwbc+gryVwJMynIrz7ScTdSYg+t8M6IRHpQkfMITjSe7vAZbV6uFo8 u5UpwVnfHfxtbRrC7UeKJIIDvx6Uz8Sxtn/hlIw3IGem/SSYJPs8hrRNmVOEha19dKQZ rXpkqljH6A/RBTGMyHPaThicHr+2qNskoglUtp2uzdOzoCv8WBbgaafRak4Rs3lwKv3n RCCIgiZZUqtIPiLZAzDLuX4VXg/P2E15BWHP8rl/iSX+vNjEkNYykp/PHmodbnclWtAu 6hoAGuECw06fLzzT886idewsOXcbZ6XMuPz5VwoyK/T/7JFk7+j6GjCGnv1HwV3fqWMa 20sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739449380; x=1740054180; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r5LQvdlT1sMf3RQG3zaZimZ3xYwH68boESfP4z93+Xs=; b=N8fMo5LWbU542qJ7CnRg0YxaLVxPWkfTV8xyH7go+V1udU+dQI8P3bHoo0U0ee1NUe S/gEj1KO4pvw2W2Cd5MsRn2giXTwJ0CUsQ3FvA5kosRHc0EKcIOTC1dvGijJICo4CsQW Wk+1RJznZUI0a9HVfTn40xXaW4xlvVH7PtsSKFZVKqCN8vzUm8108Nx9lX1T4fCB2nRm mZl9f2IWW4PL5euQT0uTt4DZkw0zMJ2JrhEkgL6WnKqoWBOlgdlqRD0pwImXOzBwHLtM xbQC+u6h3MpI5o02POccgaR6D0kL8k3nErns96TOgLgNSTfMH+xZLykuUh86ui6wKf4j nLJw== X-Gm-Message-State: AOJu0Yyb73Niy5kfLx8zk0Hn5USkL8ilUtYpvPF//cltOnE3gBKO9RYD /melnFSjqg6NI80prAvQ+kVE+z/nvOEBHt5NyF9HsTitJtquqv24HJHLnNjDg0fERSLDIAIWYSz 1MiY= X-Gm-Gg: ASbGncuc2F14uu3cgmhho7e94LW2izBDzoQZZnKCbo8FKm5U9zedMR2GXpD1tsNUEal wZlPfZqh81saYp8PjUNTdPAb8lLwW19MFL6Zvb2R32NkXI6vSbwczBL4ba1opciFeacmclekKtc WAuFSPyGXSH8Ze3nx7iXY/OSro7wDbRU1pRo7coJ/zt6Wxc+/eNc6XGByIexdSDod0/dkGlI97i mVBiS+fZmyb289kBMRUtuSGhUR4irr5/MB3Uyej7Hs+Edh6s2as3qssfsLksjGGsCeXh/PJIlEZ xPhRVHlWf6qOBjvdwbN9UPfPcsr9vMsXIu2/TmHNKz76fR6zhcnYEqFrJBnw X-Google-Smtp-Source: AGHT+IEufQtYl1GZXzBN/A//tfi/4Bn39SOfFGr2GojO+YdfJtuUJ+1rvKKa3AdiJ2TXyBjfJM41ng== X-Received: by 2002:a17:907:7dab:b0:ab7:cc43:c51e with SMTP id a640c23a62f3a-aba4eba808amr304929766b.13.1739449380395; Thu, 13 Feb 2025 04:23:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v8 6/6] hw/ssi/xilinx_spi: Make device endianness configurable Date: Thu, 13 Feb 2025 13:22:17 +0100 Message-ID: <20250213122217.62654-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250213122217.62654-1-philmd@linaro.org> References: <20250213122217.62654-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1739449459906019000 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "endianness" property to select the device endianness. This property is unspecified by default, and machines need to make it explicit. Set the proper endianness on the single machine using the device. Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/ssi/xilinx_spi.c | 32 +++++++++++++++++++++-------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index 984287fdc53..21ad215e442 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -177,6 +177,7 @@ petalogix_ml605_init(MachineState *machine) SSIBus *spi; =20 dev =3D qdev_new("xlnx.xps-spi"); + qdev_prop_set_enum(dev, "endianness", endianness); qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); busdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index fd1ff12eb1d..be5baa6b350 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -25,6 +25,7 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/module.h" @@ -32,6 +33,7 @@ =20 #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" #include "hw/ssi/ssi.h" #include "qom/object.h" =20 @@ -83,6 +85,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI) struct XilinxSPI { SysBusDevice parent_obj; =20 + EndianMode model_endianness; MemoryRegion mmio; =20 qemu_irq irq; @@ -313,14 +316,17 @@ done: xlx_spi_update_irq(s); } =20 -static const MemoryRegionOps spi_ops =3D { - .read =3D spi_read, - .write =3D spi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 - } +static const MemoryRegionOps spi_ops[2] =3D { + [0 ... 1] =3D { + .read =3D spi_read, + .write =3D spi_write, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + }, + [0].endianness =3D DEVICE_LITTLE_ENDIAN, + [1].endianness =3D DEVICE_BIG_ENDIAN, }; =20 static void xilinx_spi_realize(DeviceState *dev, Error **errp) @@ -329,6 +335,12 @@ static void xilinx_spi_realize(DeviceState *dev, Error= **errp) XilinxSPI *s =3D XILINX_SPI(dev); int i; =20 + if (s->model_endianness =3D=3D ENDIAN_MODE_UNSPECIFIED) { + error_setg(errp, TYPE_XILINX_SPI " property 'endianness'" + " must be set to 'big' or 'little'"); + return; + } + DB_PRINT("\n"); =20 s->spi =3D ssi_create_bus(dev, "spi"); @@ -339,7 +351,8 @@ static void xilinx_spi_realize(DeviceState *dev, Error = **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } =20 - memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, + memory_region_init_io(&s->mmio, OBJECT(s), + &spi_ops[s->model_endianness =3D=3D ENDIAN_MODE_= BIG], s, "xilinx-spi", R_MAX * 4); sysbus_init_mmio(sbd, &s->mmio); =20 @@ -362,6 +375,7 @@ static const VMStateDescription vmstate_xilinx_spi =3D { }; =20 static const Property xilinx_spi_properties[] =3D { + DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxSPI, model_endianness= ), DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1), }; =20 --=20 2.47.1