From nobody Sat Apr 5 01:30:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1739417998; cv=none; d=zohomail.com; s=zohoarc; b=h08PsRRhkATzE+lWYKYwUJ0JKbujk4Prxz0dj/vEKAlNYs1id6NRHwIuSzBI1HiFEz4HDdfVV0IA4yxT5ffiInjDPn2mN4Yq9rJmm3psm/X2eu/Nl6TJkAlDtR4CL3aXqbm8OnME4Hs8F7uzRpGfMD6k6+o495i5wy6J68wGMZQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739417998; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=MjMaLAE7qydB6/nZ1diFusBT4eXLog2cOspq43XMvqc=; b=iusrRJrptfXQzbeFZqZxfEeX+/czaJUBSbPO2dyy9NX9mG+2ONJP0YLV2GIrx6FWVoNOnQkqzI0cFXAlg4MllLG1WtG9Hn0M+HfaY8L8wKlOyDsmTdSKQgaUhDeRondeVTh6nFVhzVIqks+TWvxhy+2jTCgmeztWosP5obILsNQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1739417998699669.5264031185222; Wed, 12 Feb 2025 19:39:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiQ1c-0007J8-9G; Wed, 12 Feb 2025 22:36:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiQ14-0007A9-RW; Wed, 12 Feb 2025 22:35:54 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiQ13-0000hG-I8; Wed, 12 Feb 2025 22:35:54 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 13 Feb 2025 11:35:34 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 13 Feb 2025 11:35:34 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v3 06/28] hw/intc/aspeed: Support different memory region ops Date: Thu, 13 Feb 2025 11:35:09 +0800 Message-ID: <20250213033531.3367697-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250213033531.3367697-1-jamin_lin@aspeedtech.com> References: <20250213033531.3367697-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1739418000906019000 Content-Type: text/plain; charset="utf-8" The previous implementation set the "aspeed_intc_ops" struct, containing re= ad and write callbacks, to be used when I/O is performed on the INTC region. Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used for INTC (CPU Die). To support the INTCIO (IO Die) model, introduces a new "reg_ops" class attribute. This allows setting different memory region operations to support different INTC models. Will introduce "aspeed_intcio_read" and "aspeed_intcio_write" callback functions are used for INTCIO. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/aspeed_intc.c | 5 ++++- include/hw/intc/aspeed_intc.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 91d8edb261..cc2426fbac 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -340,7 +340,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error= **errp) =20 sysbus_init_mmio(sbd, &s->iomem_container); =20 - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, + memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s, TYPE_ASPEED_INTC ".regs", aic->reg_size); =20 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); @@ -358,11 +358,14 @@ static void aspeed_intc_realize(DeviceState *dev, Err= or **errp) static void aspeed_intc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); =20 dc->desc =3D "ASPEED INTC Controller"; dc->realize =3D aspeed_intc_realize; device_class_set_legacy_reset(dc, aspeed_intc_reset); dc->vmsd =3D NULL; + + aic->reg_ops =3D &aspeed_intc_ops; } =20 static const TypeInfo aspeed_intc_info =3D { diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index ecaeb15aea..749d7c55be 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -43,6 +43,7 @@ struct AspeedINTCClass { uint32_t num_ints; uint64_t mem_size; uint64_t reg_size; + const MemoryRegionOps *reg_ops; }; =20 #endif /* ASPEED_INTC_H */ --=20 2.34.1