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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
<leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel
Stanley" <joel@jms.id.au>, "open list:All patches CC here"
<qemu-devel@nongnu.org>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v3 16/28] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC
Interrupt Mapping
Date: Thu, 13 Feb 2025 11:35:19 +0800
Message-ID: <20250213033531.3367697-17-jamin_lin@aspeedtech.com>
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Reply-to: Jamin Lin <jamin_lin@aspeedtech.com>
From: Jamin Lin via <qemu-devel@nongnu.org>
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Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 82 ++++++++++++++++++++++++++---------------
1 file changed, 52 insertions(+), 30 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 775e953afd..ca4b620a1d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -119,21 +119,27 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D {
};
=20
/* GICINT 128 */
-static const int aspeed_soc_ast2700_gic128_intcmap[] =3D {
+/* GICINT 192 */
+static const int ast2700_gic128_gic192_intcmap[] =3D {
[ASPEED_DEV_LPC] =3D 0,
[ASPEED_DEV_IBT] =3D 2,
[ASPEED_DEV_KCS] =3D 4,
};
=20
+/* GICINT 129 */
+/* GICINT 193 */
+
/* GICINT 130 */
-static const int aspeed_soc_ast2700_gic130_intcmap[] =3D {
+/* GICINT 194 */
+static const int ast2700_gic130_gic194_intcmap[] =3D {
[ASPEED_DEV_I2C] =3D 0,
[ASPEED_DEV_ADC] =3D 16,
[ASPEED_DEV_GPIO] =3D 18,
};
=20
/* GICINT 131 */
-static const int aspeed_soc_ast2700_gic131_intcmap[] =3D {
+/* GICINT 195 */
+static const int ast2700_gic131_gic195_intcmap[] =3D {
[ASPEED_DEV_I3C] =3D 0,
[ASPEED_DEV_WDT] =3D 16,
[ASPEED_DEV_FMC] =3D 25,
@@ -141,7 +147,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] =
=3D {
};
=20
/* GICINT 132 */
-static const int aspeed_soc_ast2700_gic132_intcmap[] =3D {
+/* GICINT 196 */
+static const int ast2700_gic132_gic196_intcmap[] =3D {
[ASPEED_DEV_ETH1] =3D 0,
[ASPEED_DEV_ETH2] =3D 1,
[ASPEED_DEV_ETH3] =3D 2,
@@ -160,24 +167,26 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] =
=3D {
};
=20
/* GICINT 133 */
-static const int aspeed_soc_ast2700_gic133_intcmap[] =3D {
+/* GICINT 197 */
+static const int ast2700_gic133_gic197_intcmap[] =3D {
[ASPEED_DEV_SDHCI] =3D 1,
[ASPEED_DEV_PECI] =3D 4,
};
=20
/* GICINT 128 ~ 136 */
+/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
const int *ptr;
};
=20
-static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] =3D=
{
- {128, aspeed_soc_ast2700_gic128_intcmap},
+static const struct gic_intc_irq_info ast2700_gic_intcmap[] =3D {
+ {128, ast2700_gic128_gic192_intcmap},
{129, NULL},
- {130, aspeed_soc_ast2700_gic130_intcmap},
- {131, aspeed_soc_ast2700_gic131_intcmap},
- {132, aspeed_soc_ast2700_gic132_intcmap},
- {133, aspeed_soc_ast2700_gic133_intcmap},
+ {130, ast2700_gic130_gic194_intcmap},
+ {131, ast2700_gic131_gic195_intcmap},
+ {132, ast2700_gic132_gic196_intcmap},
+ {133, ast2700_gic133_gic197_intcmap},
{134, NULL},
{135, NULL},
{136, NULL},
@@ -189,11 +198,11 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCS=
tate *s, int dev)
AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
int i;
=20
- for (i =3D 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] =3D=3D aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
+ ast2700_gic_intcmap[i].ptr[dev]);
}
}
=20
@@ -207,16 +216,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe=
edSoCState *s, int dev,
AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
int i;
=20
- for (i =3D 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] =3D=3D aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
+ ast2700_gic_intcmap[i].ptr[dev] + inde=
x);
}
}
=20
/*
- * Invalid orgate index, device irq should be 128 to 136.
+ * Invalid OR gate index, device IRQ should be between 128 to 136
+ * and 192 to 201.
*/
g_assert_not_reached();
}
@@ -481,7 +491,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev=
, Error **errp)
Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev);
AspeedSoCState *s =3D ASPEED_SOC(dev);
AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
- AspeedINTCClass *ic =3D ASPEED_INTC_GET_CLASS(&a->intc);
g_autofree char *sram_name =3D NULL;
qemu_irq irq;
=20
@@ -519,17 +528,18 @@ static void aspeed_soc_ast2700_realize(DeviceState *d=
ev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
sc->memmap[ASPEED_DEV_INTC]);
=20
- /* source orgates -> INTC */
- for (i =3D 0; i < ic->num_inpins; i++) {
+ /* irq sources -> orgates -> INTC */
+ for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
- qdev_get_gpio_in(DEVICE(&a->intc), i));
+ qdev_get_gpio_in(DEVICE(&a->intc), i));
}
=20
+ /* INTC -> GIC192 - GIC201 */
/* INTC -> GIC128 - GIC136 */
- for (i =3D 0; i < ic->num_outpins; i++) {
+ for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc)->num_outpins; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
qdev_get_gpio_in(DEVICE(&a->gic),
- aspeed_soc_ast2700_gic_intcmap[i].irq));
+ ast2700_gic_intcmap[i].irq));
}
=20
/* SRAM */
@@ -680,10 +690,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *d=
ev, Error **errp)
for (i =3D 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
/*
* The AST2700 I2C controller has one source INTC per bus.
- * I2C buses interrupt are connected to GICINT130_INTC
- * from bit 0 to bit 15.
- * I2C bus 0 is connected to GICINT130_INTC at bit 0.
- * I2C bus 15 is connected to GICINT130_INTC at bit 15.
+ *
+ * For AST2700 A0:
+ * I2C bus interrupts are connected to the OR gate from bit 0 to b=
it
+ * 15, and the OR gate output pin is connected to the input pin of
+ * GICINT130 of INTC (CPU Die). Then, the output pin is connected =
to
+ * the GIC.
+ *
+ * For AST2700 A1:
+ * I2C bus interrupts are connected to the OR gate from bit 0 to b=
it
+ * 15, and the OR gate output pin is connected to the input pin of
+ * GICINT194 of INTCIO (IO Die). Then, the output pin is connected
+ * to the INTC (CPU Die) input pin, and its output pin is connected
+ * to the GIC.
+ *
+ * I2C bus 0 is connected to the OR gate at bit 0.
+ * I2C bus 15 is connected to the OR gate at bit 15.
*/
irq =3D aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
--=20
2.34.1