From nobody Sat Apr 5 01:33:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1739418055; cv=none; d=zohomail.com; s=zohoarc; b=JCo2Ir8On9YF7jBgO+56Kl7jsvfAJhJhynKghKkp0tfWfRqgi0c8HPFA5uk3rFgCH9wBpIr5aW+O7yZgbbehiHW9A4lqqsqZm5Z7UsjResBttDtHdoPzJ748X33rXJ4tCG4OYuiYES6d05FDtpXwMKajQCsALFApHK8bBW0hS6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739418055; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=lErHmpJ+T5uLBGxd/2QewqZtmiA72ekEQfPgHFysZZI=; b=kDBe9BX1hWLsYAy68fhPbWodMty9PqqZPJp8mjpnDf/QztnX7SFTVjnZYgaQvYEoEfvgxJ7SHmfHgafhuVR/YtRHNxKNEY9/7EnkwZn54GnHWHL+/GrKiSS+w6GvSoKOQSsrkYMJJITyfswxXEyYCLcoJjYPVs9EIMU6EkMZV44= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1739418055541503.91570361128515; Wed, 12 Feb 2025 19:40:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tiQ1m-0007dq-Q6; Wed, 12 Feb 2025 22:36:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiQ1k-0007az-RY; Wed, 12 Feb 2025 22:36:36 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tiQ1j-0000l1-2p; Wed, 12 Feb 2025 22:36:36 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 13 Feb 2025 11:35:37 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 13 Feb 2025 11:35:37 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v3 15/28] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 Date: Thu, 13 Feb 2025 11:35:18 +0800 Message-ID: <20250213033531.3367697-16-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250213033531.3367697-1-jamin_lin@aspeedtech.com> References: <20250213033531.3367697-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1739418057017019000 Content-Type: text/plain; charset="utf-8" According to the design of the AST2600, it has a Silicon Revision ID Regist= er, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x0503= 0303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in SCU014. The value of "s->silicon_rev" is set by the SOC layer via the "silicon-rev" property. However, the design of the AST2700 is different. There are two SCU controll= ers: SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision = ID register (SCU1_000) and combines them into a 64-bit value. The combined value of SCU0_000[23:16] and SCU1_000[23:16] represents the si= licon revision. For example, the AST2700-A1 revision is "0x0601010306010103", whe= re SCU0_000 should be 06010103 and SCU1_000 should be 06010103. Reference: https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/a= rm/mach-aspeed/ast2700/cpu-info.c Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 2d9fe78926..b45a36a555 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -911,7 +911,6 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops =3D= { }; =20 static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] =3D { - [AST2700_SILICON_REV] =3D AST2700_A0_SILICON_REV, [AST2700_HW_STRAP1] =3D 0x00000800, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, @@ -940,6 +939,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(dev); =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); + s->regs[AST2700_SILICON_REV] =3D s->silicon_rev; } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) @@ -1032,7 +1032,6 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops= =3D { }; =20 static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] =3D= { - [AST2700_SILICON_REV] =3D 0x06000003, [AST2700_HW_STRAP1] =3D 0x00000504, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, --=20 2.34.1