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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd1af07sm17390101f8f.15.2025.02.12.03.24.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 03:24:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739359480; x=1739964280; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qque2XZ1dU81iGdYR24fO3GVnw9hhnz4b3BIk7lxH2E=; b=yQ2EoxxRFl1NA60u4SQfy/rFNhk0EmKdr8fU9RceuC6mUBJD5eAKLG2KaIF5RHpotI /7NmB9FqIQa2TierTWrp4bJ4giBOz7Y+DZGxYJtZzzSoj/XxezFS1561czHlFKluiqtY mBPoEUNfh3I8nPdtKV/nvNXxy+zedYlDfaGsoaJ71ftqHXLA/WcPXlwz+pHNx5Mf7yh2 w7qj11ES5xex49rUPn85YOaf4G4IqOdJ/DJNIyqiYrVb2ImUPBsxvJm5FLvrnVxExx9V 9vPq0yEzbJ/bRZwerfNXYSeXpU9ZFgJJ7yg9jCN3wlhi6t5pzkBYBnYPniMRYnCLsbqT dmvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739359480; x=1739964280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qque2XZ1dU81iGdYR24fO3GVnw9hhnz4b3BIk7lxH2E=; b=UApQVN+gUJVXL/KTlDaOAgRc0Ab73MfPT4ey1Pd8m/1e1MOeEAEnP73bToQOxQBVyx 8Rzz6Zx9unls8ws0JbrxZJS0VcxFUkvinGAEbtxlugrxTDvJDRuLmwMiTWBvFGx4ppxk e+SPkSIsdflyAqSuaUsQhr8wHKEN5GzGio1+2YzMI8Gmffz6It5Vgi/9z97GV20VwTa4 pC9jjvOBYQ0U7nNHuIrVPI3OeLrg+jEp82jHMHaiohW1gSlCTTQ3ytp0Ro3xN5DQ8MNZ ZuFkpxJblSW2uhs8ALbMRjQCIp1MFIiKie5CWoImdytu1DxxnKZfEzY4PXZWvb1F+JSD Q0xw== X-Gm-Message-State: AOJu0Yx1MVs1/X1VsqJ0IH9DNOOSRim9RPBZZ23Dce6B8UplHwcevS15 i2s+Kc35r4NQ3wisV7X+TMecczo+eIus1yaEZwi9HO+HiBD4YBsGCxnt2lGMBnP64Fvwn2MTQrK gR1A= X-Gm-Gg: ASbGncs68h87cUetVnZdGgY/pYSNV1xuA/KaLDDOCD+aPKHRSirZtlWKO5WPmhiZCXU dtKCLk5sAjDAcWyi1sKe4ZsfdRlbda11QCFTxGEsOgC626X+yYPs/tywC+jb8onYGpUYYpePCak hZeIpeeVf2ta/QuSLeyFGwl1JgjZ/kYqDMP4eTHIRiyuhfJpZmJDCMNZ/xo1vsDFeQRst6kNKjD 4D5LxzxIEqUI+P8eJVtl9DGBkl15kXxgo92nN5nj3RWD6who58+lnp/cJ6W8eD0DlPkStbdegcU BFb0/ntDDIVLgjkI90tTGcNqUZcvhdpwhX4qlO2zdTciiIpExUFlhJnCyZNCuq0rYw== X-Google-Smtp-Source: AGHT+IFNDzo6COMI9HZI6tOI90FY8EHZldwBzXiKq59lW+yhMmkMCOTE7aGpWlaD48acOBbaTA8qLw== X-Received: by 2002:a05:600c:3ba8:b0:439:4832:325f with SMTP id 5b1f17b1804b1-43958160560mr23189195e9.1.1739359479876; Wed, 12 Feb 2025 03:24:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, "Edgar E. Iglesias" , Alistair Francis , Richard Henderson , Thomas Huth , Markus Armbruster , qemu-arm@nongnu.org, =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 05/11] hw/char/xilinx_uartlite: Make device endianness configurable Date: Wed, 12 Feb 2025 12:24:07 +0100 Message-ID: <20250212112413.37553-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212112413.37553-1-philmd@linaro.org> References: <20250212112413.37553-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1739359709613019000 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/char/xilinx_uartlite.c | 34 ++++++++++++++++-------- hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 + hw/riscv/microblaze-v-generic.c | 1 + 3 files changed, 25 insertions(+), 11 deletions(-) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 56955e0d74a..907fb33c6c0 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qapi/error.h" #include "hw/char/xilinx_uartlite.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -57,6 +58,7 @@ struct XilinxUARTLite { SysBusDevice parent_obj; =20 + EndianMode model_endianness; MemoryRegion mmio; CharBackend chr; qemu_irq irq; @@ -166,17 +168,21 @@ uart_write(void *opaque, hwaddr addr, uart_update_irq(s); } =20 -static const MemoryRegionOps uart_ops =3D { - .read =3D uart_read, - .write =3D uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 4 - } +static const MemoryRegionOps uart_ops[2] =3D { + [0 ... 1] =3D { + .read =3D uart_read, + .write =3D uart_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + }, + [ENDIAN_MODE_BIG].endianness =3D DEVICE_BIG_ENDIAN, + [ENDIAN_MODE_LITTLE].endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static const Property xilinx_uartlite_properties[] =3D { + DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxUARTLite, model_endia= nness), DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), }; =20 @@ -214,6 +220,15 @@ static void xilinx_uartlite_realize(DeviceState *dev, = Error **errp) { XilinxUARTLite *s =3D XILINX_UARTLITE(dev); =20 + if (s->model_endianness =3D=3D ENDIAN_MODE_UNSPECIFIED) { + error_setg(errp, TYPE_XILINX_UARTLITE " property 'endianness'" + " must be set to 'big' or 'little'"); + return; + } + + memory_region_init_io(&s->mmio, OBJECT(dev), + &uart_ops[s->model_endianness], + s, "xlnx.xps-uartlite", R_MAX * 4); qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, NULL, s, NULL, true); } @@ -223,9 +238,6 @@ static void xilinx_uartlite_init(Object *obj) XilinxUARTLite *s =3D XILINX_UARTLITE(obj); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, &uart_ops, s, - "xlnx.xps-uartlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } =20 diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index caaea222a8c..bdba2006b72 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -109,6 +109,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } =20 dev =3D qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_enum(dev, "endianness", endianness); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index 3c79f5733b2..d8e67906d26 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -92,6 +92,7 @@ static void mb_v_generic_init(MachineState *machine) =20 /* Uartlite */ dev =3D qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE); qdev_prop_set_chr(dev, "chardev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); --=20 2.47.1