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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 64/68] target/arm: Remove fp_status_a32
Date: Tue, 11 Feb 2025 16:25:50 +0000
Message-Id: <20250211162554.4135349-65-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Replace with fp_status[FPST_A32]. As this was the last of the
old structures, we can remove the anonymous union and struct.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Message-id: 20250129013857.135256-15-richard.henderson@linaro.org
[PMM: tweak to account for change to is_ebf()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 7 +------
target/arm/cpu.c | 2 +-
target/arm/tcg/vec_helper.c | 2 +-
target/arm/vfp_helper.c | 18 +++++++++---------
4 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0d8b99bd8af..6f6cf5c888b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -687,12 +687,7 @@ typedef struct CPUArchState {
uint32_t scratch[8];
=20
/* There are a number of distinct float control structures. */
- union {
- float_status fp_status[FPST_COUNT];
- struct {
- float_status fp_status_a32;
- };
- };
+ float_status fp_status[FPST_COUNT];
=20
uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f04f28b681a..656070afb59 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -550,7 +550,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t=
ype)
set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]);
set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]);
set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]);
- arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]);
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 215affc2711..2da44ae7102 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2951,7 +2951,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp, =
float_status *oddstatusp)
*/
bool ebf =3D is_a64(env) && env->vfp.fpcr & FPCR_EBF;
=20
- *statusp =3D is_a64(env) ? env->vfp.fp_status[FPST_A64] : env->vfp.fp_=
status_a32;
+ *statusp =3D env->vfp.fp_status[is_a64(env) ? FPST_A64 : FPST_A32];
set_default_nan_mode(true, statusp);
=20
if (ebf) {
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index e6b4f63401b..4d1b697a665 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -117,7 +117,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
{
uint32_t a32_flags =3D 0, a64_flags =3D 0;
=20
- a32_flags |=3D get_float_exception_flags(&env->vfp.fp_status_a32);
+ a32_flags |=3D get_float_exception_flags(&env->vfp.fp_status[FPST_A32]=
);
a32_flags |=3D get_float_exception_flags(&env->vfp.fp_status[FPST_STD]=
);
/* FZ16 does not generate an input denormal exception. */
a32_flags |=3D (get_float_exception_flags(&env->vfp.fp_status[FPST_A32=
_F16])
@@ -155,7 +155,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMStat=
e *env)
* values. The caller should have arranged for env->vfp.fpsr to
* be the architecturally up-to-date exception flag information first.
*/
- set_float_exception_flags(0, &env->vfp.fp_status_a32);
+ set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]);
@@ -198,7 +198,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint=
32_t val, uint32_t mask)
i =3D float_round_to_zero;
break;
}
- set_float_rounding_mode(i, &env->vfp.fp_status_a32);
+ set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32]);
set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]);
set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]);
set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]);
@@ -216,10 +216,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, ui=
nt32_t val, uint32_t mask)
}
if (changed & FPCR_FZ) {
bool ftz_enabled =3D val & FPCR_FZ;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32]);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]);
/* FIZ is A64 only so FZ always makes A32 code flush inputs to zer=
o */
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32=
]);
}
if (changed & (FPCR_FZ | FPCR_AH | FPCR_FIZ)) {
/*
@@ -232,7 +232,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint=
32_t val, uint32_t mask)
}
if (changed & FPCR_DN) {
bool dnan_enabled =3D val & FPCR_DN;
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F1=
6]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F1=
6]);
@@ -497,8 +497,8 @@ void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMSt=
ate *env) \
FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
}
DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status[FPST_A32_F16])
-DO_VFP_cmp(s, float32, float32, fp_status_a32)
-DO_VFP_cmp(d, float64, float64, fp_status_a32)
+DO_VFP_cmp(s, float32, float32, fp_status[FPST_A32])
+DO_VFP_cmp(d, float64, float64, fp_status[FPST_A32])
#undef DO_VFP_cmp
=20
/* Integer to float and float to integer conversions */
@@ -1385,7 +1385,7 @@ uint64_t HELPER(fjcvtzs)(float64 value, float_status =
*status)
=20
uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
{
- uint64_t pair =3D HELPER(fjcvtzs)(value, &env->vfp.fp_status_a32);
+ uint64_t pair =3D HELPER(fjcvtzs)(value, &env->vfp.fp_status[FPST_A32]=
);
uint32_t result =3D pair;
uint32_t z =3D (pair >> 32) =3D=3D 0;
=20
--=20
2.34.1