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From: Rob Bradford <rbradford@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bmeng.cn@gmail.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>, qemu-riscv@nongnu.org,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Alistair Francis <alistair.francis@wdc.com>,
Rob Bradford <rbradford@rivosinc.com>
Subject: [PATCH] target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry
Date: Mon, 10 Feb 2025 15:37:13 +0000
Message-ID: <20250210153713.343626-1-rbradford@rivosinc.com>
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When running in TOR mode (Top of Range) the next PMP entry controls
whether the entry is locked. However simply checking if the PMP_LOCK bit
is set is not sufficient with the Smepmp extension which now provides a
bit (mseccfg.RLB (Rule Lock Bypass)) to disregard the lock bits. In
order to respect this bit use the convenience pmp_is_locked() function
rather than directly checking PMP_LOCK since this function checks
mseccfg.RLB.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index a185c246d6..85ab270dad 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -524,7 +524,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add=
r_index,
uint8_t pmp_cfg =3D env->pmp_state.pmp[addr_index + 1].cfg_reg;
is_next_cfg_tor =3D PMP_AMATCH_TOR =3D=3D pmp_get_a_field(pmp_=
cfg);
=20
- if (pmp_cfg & PMP_LOCK && is_next_cfg_tor) {
+ if (pmp_is_locked(env, addr_index + 1) && is_next_cfg_tor) {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - pmpcfg + 1 locked\=
n");
return;
--=20
2.48.1