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Sat, 08 Feb 2025 08:39:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 4/7] hw/char/pl011: Trace FIFO enablement Date: Sat, 8 Feb 2025 17:39:08 +0100 Message-ID: <20250208163911.54522-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250208163911.54522-1-philmd@linaro.org> References: <20250208163911.54522-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1739032858244019000 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/char/pl011.c | 4 +++- hw/char/trace-events | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index b9c9e5b5983..447f185e2d5 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -148,6 +148,7 @@ static bool pl011_loopback_enabled(PL011State *s) =20 static bool pl011_is_fifo_enabled(PL011State *s) { + trace_pl011_fifo_is_enabled((s->lcr & LCR_FEN) !=3D 0); return (s->lcr & LCR_FEN) !=3D 0; } =20 @@ -464,8 +465,9 @@ static void pl011_write(void *opaque, hwaddr offset, pl011_trace_baudrate_change(s); break; case 11: /* UARTLCR_H */ - /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & LCR_FEN) { + /* Reset the FIFO state on FIFO enable or disable */ + trace_pl011_fifo_enable(value & LCR_FEN); pl011_reset_rx_fifo(s); pl011_reset_tx_fifo(s); } diff --git a/hw/char/trace-events b/hw/char/trace-events index 3d07866be5c..dd635ac6012 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -63,6 +63,8 @@ pl011_read(uint32_t addr, uint32_t value, const char *reg= name) "addr 0x%03x valu pl011_read_fifo(int read_count) "FIFO read, read_count now %d" pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%0= 3x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_co= unt %d returning %d" +pl011_fifo_enable(bool enable) "enable:%u" +pl011_fifo_is_enabled(bool enabled) "enabled:%u" pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count = now %d" pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]" --=20 2.47.1