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Thu, 06 Feb 2025 14:12:27 -0800 (PST) Date: Thu, 6 Feb 2025 14:11:58 -0800 In-Reply-To: <20250206221203.4187217-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20250206221203.4187217-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.48.1.502.g6dc24dfdaf-goog Message-ID: <20250206221203.4187217-13-wuhaotsh@google.com> Subject: [PATCH v4 12/17] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, chli30@nuvoton.corp-partner.google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, philmd@linaro.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::104a; envelope-from=3yzOlZwgKCgw86tm054ts00sxq.o0y2qy6-pq7qxz0zsz6.03s@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x104a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1738880244045019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These 2 values are different between NPCM7XX and NPCM8XX CLKs. So we add them to the class and assign different values to them. Reviewed-by: Peter Maydell Signed-off-by: Hao Wu --- hw/misc/npcm_clk.c | 18 ++++++++++++------ hw/misc/npcm_gcr.c | 2 ++ include/hw/misc/npcm_clk.h | 9 ++++++++- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 0ecf0df3bb..78144b14e3 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -81,7 +81,7 @@ enum NPCM7xxCLKRegisters { * All are loaded on power-up reset. CLKENx and SWRSTR should also be load= ed on * core domain reset, but this reset type is not yet supported by QEMU. */ -static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] =3D { +static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] =3D { [NPCM7XX_CLK_CLKEN1] =3D 0xffffffff, [NPCM7XX_CLK_CLKSEL] =3D 0x004aaaaa, [NPCM7XX_CLK_CLKDIV1] =3D 0x5413f855, @@ -728,10 +728,11 @@ static uint64_t npcm_clk_read(void *opaque, hwaddr of= fset, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); NPCMCLKState *s =3D opaque; + NPCMCLKClass *c =3D NPCM_CLK_GET_CLASS(s); int64_t now_ns; uint32_t value =3D 0; =20 - if (reg >=3D NPCM7XX_CLK_NR_REGS) { + if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -776,11 +777,12 @@ static void npcm_clk_write(void *opaque, hwaddr offse= t, { uint32_t reg =3D offset / sizeof(uint32_t); NPCMCLKState *s =3D opaque; + NPCMCLKClass *c =3D NPCM_CLK_GET_CLASS(s); uint32_t value =3D v; =20 trace_npcm_clk_write(offset, value); =20 - if (reg >=3D NPCM7XX_CLK_NR_REGS) { + if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -870,10 +872,10 @@ static const struct MemoryRegionOps npcm_clk_ops =3D { static void npcm_clk_enter_reset(Object *obj, ResetType type) { NPCMCLKState *s =3D NPCM_CLK(obj); + NPCMCLKClass *c =3D NPCM_CLK_GET_CLASS(s); =20 - QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); - - memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); + g_assert(sizeof(s->regs) >=3D c->nr_regs * sizeof(uint32_t)); + memcpy(s->regs, c->cold_reset_values, sizeof(s->regs)); s->ref_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); npcm7xx_clk_update_all_clocks(s); /* @@ -1045,11 +1047,14 @@ static void npcm_clk_class_init(ObjectClass *klass,= void *data) =20 static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) { + NPCMCLKClass *c =3D NPCM_CLK_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END !=3D NPCM7XX_CLK_NR_REGS); dc->desc =3D "NPCM7xx Clock Control Registers"; + c->nr_regs =3D NPCM7XX_CLK_NR_REGS; + c->cold_reset_values =3D npcm7xx_cold_reset_values; } =20 static const TypeInfo npcm7xx_clk_pll_info =3D { @@ -1081,6 +1086,7 @@ static const TypeInfo npcm_clk_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(NPCMCLKState), .instance_init =3D npcm_clk_init, + .class_size =3D sizeof(NPCMCLKClass), .class_init =3D npcm_clk_class_init, .abstract =3D true, }; diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index d644d7ddd5..5930a88f28 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -215,6 +215,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offs= et, unsigned size) break; =20 case 8: + g_assert(!(reg & 1)); value =3D deposit64(s->regs[reg], 32, 32, s->regs[reg + 1]); break; =20 @@ -270,6 +271,7 @@ static void npcm_gcr_write(void *opaque, hwaddr offset, break; =20 case 8: + g_assert(!(reg & 1)); s->regs[reg] =3D value; s->regs[reg + 1] =3D extract64(v, 32, 32); break; diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index db03b46a52..f47614ac8d 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -175,8 +175,15 @@ struct NPCMCLKState { Clock *clkref; }; =20 +typedef struct NPCMCLKClass { + SysBusDeviceClass parent; + + size_t nr_regs; + const uint32_t *cold_reset_values; +} NPCMCLKClass; + #define TYPE_NPCM_CLK "npcm-clk" -OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK) +OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" =20 #endif /* NPCM_CLK_H */ --=20 2.48.1.502.g6dc24dfdaf-goog