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Thu, 06 Feb 2025 10:27:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMSizYmKgIPyTmJ6wZJxCyoK28lewewEd9WDUduFDWqDH0CLO5NNmT7Lqkn+mPAyOLMB3ObA== X-Received: by 2002:a05:600c:4748:b0:434:e9ee:c1e with SMTP id 5b1f17b1804b1-439249e6676mr4050255e9.31.1738866472210; Thu, 06 Feb 2025 10:27:52 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 18/22] target/riscv: convert TT Ascalon to RISCVCPUDef Date: Thu, 6 Feb 2025 19:27:06 +0100 Message-ID: <20250206182711.2420505-19-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250206182711.2420505-1-pbonzini@redhat.com> References: <20250206182711.2420505-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1738866575546019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 127 +++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b0bc5e4503f..b2b9b4f6e39 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -525,72 +525,6 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } =20 -/* Tenstorrent Ascalon */ -static void rv64_tt_ascalon_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); - env->priv_ver =3D PRIV_VERSION_1_13_0; - - /* Enable ISA extensions */ - cpu->cfg.mmu =3D true; - cpu->cfg.vlenb =3D 256 >> 3; - cpu->cfg.elen =3D 64; - cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; - cpu->cfg.rvv_ma_all_1s =3D true; - cpu->cfg.rvv_ta_all_1s =3D true; - cpu->cfg.misa_w =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.cbom_blocksize =3D 64; - cpu->cfg.cbop_blocksize =3D 64; - cpu->cfg.cboz_blocksize =3D 64; - cpu->cfg.ext_zic64b =3D true; - cpu->cfg.ext_zicbom =3D true; - cpu->cfg.ext_zicbop =3D true; - cpu->cfg.ext_zicboz =3D true; - cpu->cfg.ext_zicntr =3D true; - cpu->cfg.ext_zicond =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zihintntl =3D true; - cpu->cfg.ext_zihintpause =3D true; - cpu->cfg.ext_zihpm =3D true; - cpu->cfg.ext_zimop =3D true; - cpu->cfg.ext_zawrs =3D true; - cpu->cfg.ext_zfa =3D true; - cpu->cfg.ext_zfbfmin =3D true; - cpu->cfg.ext_zfh =3D true; - cpu->cfg.ext_zfhmin =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmop =3D true; - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbs =3D true; - cpu->cfg.ext_zkt =3D true; - cpu->cfg.ext_zvbb =3D true; - cpu->cfg.ext_zvbc =3D true; - cpu->cfg.ext_zvfbfmin =3D true; - cpu->cfg.ext_zvfbfwma =3D true; - cpu->cfg.ext_zvfh =3D true; - cpu->cfg.ext_zvfhmin =3D true; - cpu->cfg.ext_zvkng =3D true; - cpu->cfg.ext_smaia =3D true; - cpu->cfg.ext_smstateen =3D true; - cpu->cfg.ext_ssaia =3D true; - cpu->cfg.ext_sscofpmf =3D true; - cpu->cfg.ext_sstc =3D true; - cpu->cfg.ext_svade =3D true; - cpu->cfg.ext_svinval =3D true; - cpu->cfg.ext_svnapot =3D true; - cpu->cfg.ext_svpbmt =3D true; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV57); -#endif -} - static void rv64_xiangshan_nanhu_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -3095,7 +3029,66 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU | RVH | RVV, + .priv_spec =3D PRIV_VERSION_1_13_0, + .vext_spec =3D VEXT_VERSION_1_00_0, + + /* ISA extensions */ + .cfg.mmu =3D true, + .cfg.vlenb =3D 256 >> 3, + .cfg.elen =3D 64, + .cfg.rvv_ma_all_1s =3D true, + .cfg.rvv_ta_all_1s =3D true, + .cfg.misa_w =3D true, + .cfg.pmp =3D true, + .cfg.cbom_blocksize =3D 64, + .cfg.cbop_blocksize =3D 64, + .cfg.cboz_blocksize =3D 64, + .cfg.ext_zic64b =3D true, + .cfg.ext_zicbom =3D true, + .cfg.ext_zicbop =3D true, + .cfg.ext_zicboz =3D true, + .cfg.ext_zicntr =3D true, + .cfg.ext_zicond =3D true, + .cfg.ext_zicsr =3D true, + .cfg.ext_zifencei =3D true, + .cfg.ext_zihintntl =3D true, + .cfg.ext_zihintpause =3D true, + .cfg.ext_zihpm =3D true, + .cfg.ext_zimop =3D true, + .cfg.ext_zawrs =3D true, + .cfg.ext_zfa =3D true, + .cfg.ext_zfbfmin =3D true, + .cfg.ext_zfh =3D true, + .cfg.ext_zfhmin =3D true, + .cfg.ext_zcb =3D true, + .cfg.ext_zcmop =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbs =3D true, + .cfg.ext_zkt =3D true, + .cfg.ext_zvbb =3D true, + .cfg.ext_zvbc =3D true, + .cfg.ext_zvfbfmin =3D true, + .cfg.ext_zvfbfwma =3D true, + .cfg.ext_zvfh =3D true, + .cfg.ext_zvfhmin =3D true, + .cfg.ext_zvkng =3D true, + .cfg.ext_smaia =3D true, + .cfg.ext_smstateen =3D true, + .cfg.ext_ssaia =3D true, + .cfg.ext_sscofpmf =3D true, + .cfg.ext_sstc =3D true, + .cfg.ext_svade =3D true, + .cfg.ext_svinval =3D true, + .cfg.ext_svnapot =3D true, + .cfg.ext_svpbmt =3D true, + + .satp_mode64 =3D VM_1_10_SV57, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), --=20 2.48.1