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From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Anton Johansson <anjo@rev.ng>,
Jason Wang <jasowang@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>,
Alistair Francis <alistair@alistair23.me>, Thomas Huth <thuth@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Peter Maydell <peter.maydell@linaro.org>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH v5 01/16] hw/intc/xilinx_intc: Make device endianness
configurable
Date: Thu, 6 Feb 2025 14:10:37 +0100
Message-ID: <20250206131052.30207-2-philmd@linaro.org>
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Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
hw/intc/xilinx_intc.c | 52 +++++++++++++++++-------
hw/microblaze/petalogix_ml605_mmu.c | 1 +
hw/microblaze/petalogix_s3adsp1800_mmu.c | 1 +
3 files changed, 40 insertions(+), 14 deletions(-)
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 6930f83907a..cd79ac4d4ff 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -3,6 +3,9 @@
*
* Copyright (c) 2009 Edgar E. Iglesias.
*
+ * https://docs.amd.com/v/u/en-US/xps_intc
+ * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a)
+ *
* Permission is hereby granted, free of charge, to any person obtaining a=
copy
* of this software and associated documentation files (the "Software"), t=
o deal
* in the Software without restriction, including without limitation the r=
ights
@@ -49,6 +52,7 @@ struct XpsIntc
{
SysBusDevice parent_obj;
=20
+ bool little_endian_model;
MemoryRegion mmio;
qemu_irq parent_irq;
=20
@@ -140,18 +144,29 @@ static void pic_write(void *opaque, hwaddr addr,
update_irq(p);
}
=20
-static const MemoryRegionOps pic_ops =3D {
- .read =3D pic_read,
- .write =3D pic_write,
- .endianness =3D DEVICE_NATIVE_ENDIAN,
- .impl =3D {
- .min_access_size =3D 4,
- .max_access_size =3D 4,
+static const MemoryRegionOps pic_ops[2] =3D {
+ [0 ... 1] =3D {
+ .read =3D pic_read,
+ .write =3D pic_write,
+ .endianness =3D DEVICE_BIG_ENDIAN,
+ .impl =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .valid =3D {
+ /*
+ * All XPS INTC registers are accessed through the PLB interfa=
ce.
+ * The base address for these registers is provided by the
+ * configuration parameter, C_BASEADDR. Each register is 32 bi=
ts
+ * although some bits may be unused and is accessed on a 4-byte
+ * boundary offset from the base address.
+ */
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
},
- .valid =3D {
- .min_access_size =3D 4,
- .max_access_size =3D 4
- }
+ [0].endianness =3D DEVICE_BIG_ENDIAN,
+ [1].endianness =3D DEVICE_LITTLE_ENDIAN,
};
=20
static void irq_handler(void *opaque, int irq, int level)
@@ -174,13 +189,21 @@ static void xilinx_intc_init(Object *obj)
=20
qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
-
- memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
- R_MAX * 4);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
}
=20
+static void xilinx_intc_realize(DeviceState *dev, Error **errp)
+{
+ XpsIntc *p =3D XILINX_INTC(dev);
+
+ memory_region_init_io(&p->mmio, OBJECT(dev),
+ &pic_ops[p->little_endian_model],
+ p, "xlnx.xps-intc",
+ R_MAX * 4);
+}
+
static const Property xilinx_intc_properties[] =3D {
+ DEFINE_PROP_BOOL("little-endian", XpsIntc, little_endian_model, true),
DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
};
=20
@@ -188,6 +211,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, =
void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(klass);
=20
+ dc->realize =3D xilinx_intc_realize;
device_class_set_props(dc, xilinx_intc_properties);
}
=20
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_=
ml605_mmu.c
index 8b44be75a22..cf3b9574db3 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -111,6 +111,7 @@ petalogix_ml605_init(MachineState *machine)
=20
=20
dev =3D qdev_new("xlnx.xps-intc");
+ qdev_prop_set_bit(dev, "little-endian", true);
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal=
ogix_s3adsp1800_mmu.c
index 2c0d8c34cd2..0506497ad0a 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -95,6 +95,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
=20
dev =3D qdev_new("xlnx.xps-intc");
+ qdev_prop_set_bit(dev, "little-endian", !TARGET_BIG_ENDIAN);
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
--=20
2.47.1