From nobody Sun Feb 8 20:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1738835626; cv=none; d=zohomail.com; s=zohoarc; b=B7f4zCnlyABlWCIhrhO8cR3kxxWcC6WBL+8/86etKnDj7Q9tbZ2Qk/+KPFJjiOFnS14dHCvrhCY8I8kNQC3S8blOG8x+A/sEnKx8bFYszWmkrgKjEolpHJBAXfNG/BMRoj5Vzsoq3WoIVO7B5Wu8T1375AB5u8I0Z6JLpevlbfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738835626; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=rHNn8ZhYLDinJ6aKgDEfgqvmGnJc94WjYWQ/vQAWcKc=; b=aWU1W+CoMRO8iU3OF+2hRGLvdC4ER67H4eBhY7QvcEtl5Kg1h3lUkthLe/l8L7r3zihj33iE0JX/cP1b5dVB6ZBquL4VBYAARhEx1uSf94tf0AeqoyHuZ49VFJLa5m6JsgHZNEy1cjf+7wfkeY7fZTFwVkDO1JJrtspN+/UMjj0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738835625736711.5289813028701; Thu, 6 Feb 2025 01:53:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfyZU-00021Q-Le; Thu, 06 Feb 2025 04:53:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfyZG-0001xi-8H; Thu, 06 Feb 2025 04:53:07 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfyZD-00051a-39; Thu, 06 Feb 2025 04:53:05 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Feb 2025 17:52:53 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Feb 2025 17:52:53 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 1/6] hw/intc/aspeed: Support setting different memory and register size Date: Thu, 6 Feb 2025 17:52:47 +0800 Message-ID: <20250206095253.928308-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250206095253.928308-1-jamin_lin@aspeedtech.com> References: <20250206095253.928308-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738835629041019100 Content-Type: text/plain; charset="utf-8" According to the AST2700 datasheet, the INTC (CPU DIE) controller has 16KB (0x4000) of register space, and the INTC_IO (I/O DIE) controller has 1KB (0= x400) of register space. Introduced a new class attribute "mem_size" to set different memory sizes f= or the INTC models in AST2700. Introduced a new class attribute "reg_size" to set different register sizes= for the INTC models in AST2700. Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 17 +++++++++++++---- include/hw/intc/aspeed_intc.h | 4 ++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 126b711b94..316885a27a 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -117,10 +117,11 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int= size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); uint32_t addr =3D offset >> 2; uint32_t value =3D 0; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (offset >=3D aic->reg_size) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", __func__, offset); @@ -143,7 +144,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, uint32_t change; uint32_t irq; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (offset >=3D aic->reg_size) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", __func__, offset); @@ -302,10 +303,16 @@ static void aspeed_intc_realize(DeviceState *dev, Err= or **errp) AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); int i; =20 + memory_region_init(&s->iomem_container, OBJECT(s), + TYPE_ASPEED_INTC ".container", aic->mem_size); + + sysbus_init_mmio(sbd, &s->iomem_container); + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, - TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS <<= 2); + TYPE_ASPEED_INTC ".regs", aic->reg_size); + + memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); =20 - sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints); =20 for (i =3D 0; i < aic->num_ints; i++) { @@ -344,6 +351,8 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, void *data) dc->desc =3D "ASPEED 2700 INTC Controller"; aic->num_lines =3D 32; aic->num_ints =3D 9; + aic->mem_size =3D 0x4000; + aic->reg_size =3D 0x2000; } =20 static const TypeInfo aspeed_2700_intc_info =3D { diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 18cb43476c..ecaeb15aea 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -25,6 +25,8 @@ struct AspeedINTCState { =20 /*< public >*/ MemoryRegion iomem; + MemoryRegion iomem_container; + uint32_t regs[ASPEED_INTC_NR_REGS]; OrIRQState orgates[ASPEED_INTC_NR_INTS]; qemu_irq output_pins[ASPEED_INTC_NR_INTS]; @@ -39,6 +41,8 @@ struct AspeedINTCClass { =20 uint32_t num_lines; uint32_t num_ints; + uint64_t mem_size; + uint64_t reg_size; }; =20 #endif /* ASPEED_INTC_H */ --=20 2.34.1 From nobody Sun Feb 8 20:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1738835650; cv=none; d=zohomail.com; s=zohoarc; b=V93H8ULypxFZ3O5YBYYdibehkmtFHZJWR1QQJKKW27ZuXCWqrK7/RAepJhF0YVnoJGOuGWicWZL8dC2IT7FGsZY9lSgfR+47ifnk+C3k6E9dbt0OCvmGk87Vg0QC0xBxdKrrxdJf396OJmEI4urath+M+nKZkpRM7gy5M+3Amw0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738835650; 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Thu, 06 Feb 2025 04:53:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfyZJ-0001yC-38; Thu, 06 Feb 2025 04:53:13 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfyZH-00051a-8C; Thu, 06 Feb 2025 04:53:08 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Feb 2025 17:52:53 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Feb 2025 17:52:53 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 2/6] hw/intc/aspeed: Introduce helper functions for enable and status registers Date: Thu, 6 Feb 2025 17:52:48 +0800 Message-ID: <20250206095253.928308-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250206095253.928308-1-jamin_lin@aspeedtech.com> References: <20250206095253.928308-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738835652157019000 Content-Type: text/plain; charset="utf-8" The behavior of the enable and status registers is almost identical between INTC(CPU Die) and INTC_IO(IO Die). To reduce duplicated code, adds "aspeed_intc_enable_handler" functions to handle enable register write behavior and "aspeed_intc_status_handler" functions to handle status register write behavior. Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 185 +++++++++++++++++++++++------------------- 1 file changed, 103 insertions(+), 82 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 316885a27a..8b1f83c878 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -114,6 +114,107 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) } } =20 +static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset, + uint64_t data) +{ + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + uint32_t addr =3D offset >> 2; + uint32_t old_enable; + uint32_t change; + uint32_t irq; + + irq =3D (offset & 0x0f00) >> 8; + + if (irq >=3D aic->num_ints) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + __func__, irq); + return; + } + + /* + * The enable registers are used to enable source interrupts. + * They also handle masking and unmasking of source interrupts + * during the execution of the source ISR. + */ + + /* disable all source interrupt */ + if (!data && !s->enable[irq]) { + s->regs[addr] =3D data; + return; + } + + old_enable =3D s->enable[irq]; + s->enable[irq] |=3D data; + + /* enable new source interrupt */ + if (old_enable !=3D s->enable[irq]) { + trace_aspeed_intc_enable(s->enable[irq]); + s->regs[addr] =3D data; + return; + } + + /* mask and unmask source interrupt */ + change =3D s->regs[addr] ^ data; + if (change & data) { + s->mask[irq] &=3D ~change; + trace_aspeed_intc_unmask(change, s->mask[irq]); + } else { + s->mask[irq] |=3D change; + trace_aspeed_intc_mask(change, s->mask[irq]); + } + + s->regs[addr] =3D data; +} + +static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset, + uint64_t data) +{ + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + uint32_t addr =3D offset >> 2; + uint32_t irq; + + irq =3D (offset & 0x0f00) >> 8; + + if (irq >=3D aic->num_ints) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + __func__, irq); + return; + } + + /* clear status */ + s->regs[addr] &=3D ~data; + + /* + * These status registers are used for notify sources ISR are executed. + * If one source ISR is executed, it will clear one bit. + * If it clear all bits, it means to initialize this register status + * rather than sources ISR are executed. + */ + if (data =3D=3D 0xffffffff) { + return; + } + + /* All source ISR execution are done */ + if (!s->regs[addr]) { + trace_aspeed_intc_all_isr_done(irq); + if (s->pending[irq]) { + /* + * handle pending source interrupt + * notify firmware which source interrupt are pending + * by setting status register + */ + s->regs[addr] =3D s->pending[irq]; + s->pending[irq] =3D 0; + trace_aspeed_intc_trigger_irq(irq, s->regs[addr]); + aspeed_intc_update(s, irq, 1); + } else { + /* clear irq */ + trace_aspeed_intc_clear_irq(irq, 0); + aspeed_intc_update(s, irq, 0); + } + } +} + static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int= size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); @@ -140,9 +241,6 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); uint32_t addr =3D offset >> 2; - uint32_t old_enable; - uint32_t change; - uint32_t irq; =20 if (offset >=3D aic->reg_size) { qemu_log_mask(LOG_GUEST_ERROR, @@ -163,45 +261,7 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, case R_GICINT134_EN: case R_GICINT135_EN: case R_GICINT136_EN: - irq =3D (offset & 0x0f00) >> 8; - - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: = %d\n", - __func__, irq); - return; - } - - /* - * These registers are used for enable sources interrupt and - * mask and unmask source interrupt while executing source ISR. - */ - - /* disable all source interrupt */ - if (!data && !s->enable[irq]) { - s->regs[addr] =3D data; - return; - } - - old_enable =3D s->enable[irq]; - s->enable[irq] |=3D data; - - /* enable new source interrupt */ - if (old_enable !=3D s->enable[irq]) { - trace_aspeed_intc_enable(s->enable[irq]); - s->regs[addr] =3D data; - return; - } - - /* mask and unmask source interrupt */ - change =3D s->regs[addr] ^ data; - if (change & data) { - s->mask[irq] &=3D ~change; - trace_aspeed_intc_unmask(change, s->mask[irq]); - } else { - s->mask[irq] |=3D change; - trace_aspeed_intc_mask(change, s->mask[irq]); - } - s->regs[addr] =3D data; + aspeed_intc_enable_handler(s, offset, data); break; case R_GICINT128_STATUS: case R_GICINT129_STATUS: @@ -212,46 +272,7 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, case R_GICINT134_STATUS: case R_GICINT135_STATUS: case R_GICINT136_STATUS: - irq =3D (offset & 0x0f00) >> 8; - - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: = %d\n", - __func__, irq); - return; - } - - /* clear status */ - s->regs[addr] &=3D ~data; - - /* - * These status registers are used for notify sources ISR are exec= uted. - * If one source ISR is executed, it will clear one bit. - * If it clear all bits, it means to initialize this register stat= us - * rather than sources ISR are executed. - */ - if (data =3D=3D 0xffffffff) { - return; - } - - /* All source ISR execution are done */ - if (!s->regs[addr]) { - trace_aspeed_intc_all_isr_done(irq); - if (s->pending[irq]) { - /* - * handle pending source interrupt - * notify firmware which source interrupt are pending - * by setting status register - */ - s->regs[addr] =3D s->pending[irq]; - s->pending[irq] =3D 0; - trace_aspeed_intc_trigger_irq(irq, s->regs[addr]); - aspeed_intc_update(s, irq, 1); - } else { - /* clear irq */ - trace_aspeed_intc_clear_irq(irq, 0); - aspeed_intc_update(s, irq, 0); - } - } + aspeed_intc_status_handler(s, offset, data); break; default: s->regs[addr] =3D data; --=20 2.34.1 From nobody Sun Feb 8 20:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1738835697; cv=none; d=zohomail.com; s=zohoarc; b=MDa7P3KAFD74e3A21Bt5SKv6yCZDApEWb1H1J3Zx/PFY1xyqfMvuQaqmjuLIAzTM4wQb5b+bTE3cRhikKAavzyKNjMBOqJdHu59F+XxuidaejI/V+dCqhfdEalMP6q8eEIz76PgVCXDEMzCNZXxBfciRmZ4N1HpSPh2/tMhilfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738835697; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Thu, 06 Feb 2025 04:53:12 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Feb 2025 17:52:54 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Feb 2025 17:52:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 3/6] hw/intc/aspeed: Add object type name to trace events for better debugging Date: Thu, 6 Feb 2025 17:52:49 +0800 Message-ID: <20250206095253.928308-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250206095253.928308-1-jamin_lin@aspeedtech.com> References: <20250206095253.928308-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738835699186019100 Content-Type: text/plain; charset="utf-8" Currently, these trace events only refer to INTC. To simplify the INTC mode= l, both INTC(CPU Die) and INTC_IO(IO Die) will share the same helper functions. However, it is difficult to recognize whether these trace events are comes = from INTC or INTC_IO. To make these trace events more readable, adds object type= name to the INTC trace events. Update trace events to include the "name" field for better identification. Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 32 +++++++++++++++++++------------- hw/intc/trace-events | 24 ++++++++++++------------ 2 files changed, 31 insertions(+), 25 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 8b1f83c878..e1e4a9fe59 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -39,6 +39,7 @@ REG32(GICINT136_STATUS, 0x1804) static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); =20 if (irq >=3D aic->num_ints) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", @@ -46,7 +47,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int ir= q, int level) return; } =20 - trace_aspeed_intc_update_irq(irq, level); + trace_aspeed_intc_update_irq(name, irq, level); qemu_set_irq(s->output_pins[irq], level); } =20 @@ -60,6 +61,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) { AspeedINTCState *s =3D (AspeedINTCState *)opaque; AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t status_addr =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); uint32_t select =3D 0; uint32_t enable; @@ -71,7 +73,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) return; } =20 - trace_aspeed_intc_set_irq(irq, level); + trace_aspeed_intc_set_irq(name, irq, level); enable =3D s->enable[irq]; =20 if (!level) { @@ -90,7 +92,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) return; } =20 - trace_aspeed_intc_select(select); + trace_aspeed_intc_select(name, select); =20 if (s->mask[irq] || s->regs[status_addr]) { /* @@ -102,14 +104,14 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) * save source interrupt to pending variable. */ s->pending[irq] |=3D select; - trace_aspeed_intc_pending_irq(irq, s->pending[irq]); + trace_aspeed_intc_pending_irq(name, irq, s->pending[irq]); } else { /* * notify firmware which source interrupt are coming * by setting status register */ s->regs[status_addr] =3D select; - trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]); + trace_aspeed_intc_trigger_irq(name, irq, s->regs[status_addr]); aspeed_intc_update(s, irq, 1); } } @@ -118,6 +120,7 @@ static void aspeed_intc_enable_handler(AspeedINTCState = *s, hwaddr offset, uint64_t data) { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; uint32_t old_enable; uint32_t change; @@ -148,7 +151,7 @@ static void aspeed_intc_enable_handler(AspeedINTCState = *s, hwaddr offset, =20 /* enable new source interrupt */ if (old_enable !=3D s->enable[irq]) { - trace_aspeed_intc_enable(s->enable[irq]); + trace_aspeed_intc_enable(name, s->enable[irq]); s->regs[addr] =3D data; return; } @@ -157,10 +160,10 @@ static void aspeed_intc_enable_handler(AspeedINTCStat= e *s, hwaddr offset, change =3D s->regs[addr] ^ data; if (change & data) { s->mask[irq] &=3D ~change; - trace_aspeed_intc_unmask(change, s->mask[irq]); + trace_aspeed_intc_unmask(name, change, s->mask[irq]); } else { s->mask[irq] |=3D change; - trace_aspeed_intc_mask(change, s->mask[irq]); + trace_aspeed_intc_mask(name, change, s->mask[irq]); } =20 s->regs[addr] =3D data; @@ -170,6 +173,7 @@ static void aspeed_intc_status_handler(AspeedINTCState = *s, hwaddr offset, uint64_t data) { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; uint32_t irq; =20 @@ -196,7 +200,7 @@ static void aspeed_intc_status_handler(AspeedINTCState = *s, hwaddr offset, =20 /* All source ISR execution are done */ if (!s->regs[addr]) { - trace_aspeed_intc_all_isr_done(irq); + trace_aspeed_intc_all_isr_done(name, irq); if (s->pending[irq]) { /* * handle pending source interrupt @@ -205,11 +209,11 @@ static void aspeed_intc_status_handler(AspeedINTCStat= e *s, hwaddr offset, */ s->regs[addr] =3D s->pending[irq]; s->pending[irq] =3D 0; - trace_aspeed_intc_trigger_irq(irq, s->regs[addr]); + trace_aspeed_intc_trigger_irq(name, irq, s->regs[addr]); aspeed_intc_update(s, irq, 1); } else { /* clear irq */ - trace_aspeed_intc_clear_irq(irq, 0); + trace_aspeed_intc_clear_irq(name, irq, 0); aspeed_intc_update(s, irq, 0); } } @@ -219,6 +223,7 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr o= ffset, unsigned int size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; uint32_t value =3D 0; =20 @@ -230,7 +235,7 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr o= ffset, unsigned int size) } =20 value =3D s->regs[addr]; - trace_aspeed_intc_read(offset, size, value); + trace_aspeed_intc_read(name, offset, size, value); =20 return value; } @@ -240,6 +245,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, { AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; =20 if (offset >=3D aic->reg_size) { @@ -249,7 +255,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, return; } =20 - trace_aspeed_intc_write(offset, size, data); + trace_aspeed_intc_write(name, offset, size, data); =20 switch (addr) { case R_GICINT128_EN: diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 3dcf147198..e9ca34755e 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -80,18 +80,18 @@ aspeed_vic_update_irq(int flags) "Raising IRQ: %d" aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%"= PRIx64 " of size %u: 0x%" PRIx32 aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" P= RIx64 " of size %u: 0x%" PRIx32 # aspeed_intc.c -aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%= " PRIx64 " of size %u: 0x%" PRIx32 -aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" = PRIx64 " of size %u: 0x%" PRIx32 -aspeed_intc_set_irq(int irq, int level) "Set IRQ %d: %d" -aspeed_intc_clear_irq(int irq, int level) "Clear IRQ %d: %d" -aspeed_intc_update_irq(int irq, int level) "Update IRQ: %d: %d" -aspeed_intc_pending_irq(int irq, uint32_t value) "Pending IRQ: %d: 0x%x" -aspeed_intc_trigger_irq(int irq, uint32_t value) "Trigger IRQ: %d: 0x%x" -aspeed_intc_all_isr_done(int irq) "All source ISR execution are done: %d" -aspeed_intc_enable(uint32_t value) "Enable: 0x%x" -aspeed_intc_select(uint32_t value) "Select: 0x%x" -aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x" -aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x" +aspeed_intc_read(const char *s, uint64_t offset, unsigned size, uint32_t v= alue) "%s: From 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_intc_write(const char *s, uint64_t offset, unsigned size, uint32_t = data) "%s: To 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_intc_set_irq(const char *s, int irq, int level) "%s: Set IRQ %d: %d" +aspeed_intc_clear_irq(const char *s, int irq, int level) "%s: Clear IRQ %d= : %d" +aspeed_intc_update_irq(const char *s, int irq, int level) "%s: Update IRQ:= %d: %d" +aspeed_intc_pending_irq(const char *s, int irq, uint32_t value) "%s: Pendi= ng IRQ: %d: 0x%x" +aspeed_intc_trigger_irq(const char *s, int irq, uint32_t value) "%s: Trigg= er IRQ: %d: 0x%x" +aspeed_intc_all_isr_done(const char *s, int irq) "%s: All source ISR execu= tion are done: %d" +aspeed_intc_enable(const char *s, uint32_t value) "%s: Enable: 0x%x" +aspeed_intc_select(const char *s, uint32_t value) "%s: Select: 0x%x" +aspeed_intc_mask(const char *s, uint32_t change, uint32_t value) "%s: Mask= : 0x%x: 0x%x" +aspeed_intc_unmask(const char *s, uint32_t change, uint32_t value) "%s: Un= Mask: 0x%x: 0x%x" =20 # arm_gic.c gic_enable_irq(int irq) "irq %d enabled" --=20 2.34.1 From nobody Sun Feb 8 20:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 6 Feb 2025 17:52:54 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Feb 2025 17:52:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 4/6] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Date: Thu, 6 Feb 2025 17:52:50 +0800 Message-ID: <20250206095253.928308-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250206095253.928308-1-jamin_lin@aspeedtech.com> References: <20250206095253.928308-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738835722969019100 Content-Type: text/plain; charset="utf-8" Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its = IRQ table and machine name. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 8 ++++---- hw/arm/aspeed_ast27x0.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d9418e2b9f..6ddfdbdeba 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1654,12 +1654,12 @@ static void ast2700_evb_i2c_init(AspeedMachineState= *bmc) TYPE_TMP105, 0x4d); } =20 -static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *d= ata) +static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void = *data) { MachineClass *mc =3D MACHINE_CLASS(oc); AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 - mc->desc =3D "Aspeed AST2700 EVB (Cortex-A35)"; + mc->desc =3D "Aspeed AST2700 A0 EVB (Cortex-A35)"; amc->soc_name =3D "ast2700-a0"; amc->hw_strap1 =3D AST2700_EVB_HW_STRAP1; amc->hw_strap2 =3D AST2700_EVB_HW_STRAP2; @@ -1795,9 +1795,9 @@ static const TypeInfo aspeed_machine_types[] =3D { .class_init =3D aspeed_minibmc_machine_ast1030_evb_class_init, #ifdef TARGET_AARCH64 }, { - .name =3D MACHINE_TYPE_NAME("ast2700-evb"), + .name =3D MACHINE_TYPE_NAME("ast2700a0-evb"), .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_ast2700_evb_class_init, + .class_init =3D aspeed_machine_ast2700a0_evb_class_init, #endif }, { .name =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 4114e15ddd..39567fcab9 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -72,7 +72,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { #define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ -static const int aspeed_soc_ast2700_irqmap[] =3D { +static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_UART0] =3D 132, [ASPEED_DEV_UART1] =3D 132, [ASPEED_DEV_UART2] =3D 132, @@ -740,7 +740,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) create_unimplemented_device("ast2700.io", 0x0, 0x4000000); } =20 -static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) +static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data) { static const char * const valid_cpu_types[] =3D { ARM_CPU_TYPE_NAME("cortex-a35"), @@ -763,7 +763,7 @@ static void aspeed_soc_ast2700_class_init(ObjectClass *= oc, void *data) sc->uarts_num =3D 13; sc->num_cpus =3D 4; sc->uarts_base =3D ASPEED_DEV_UART0; - sc->irqmap =3D aspeed_soc_ast2700_irqmap; + sc->irqmap =3D aspeed_soc_ast2700a0_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; sc->get_irq =3D aspeed_soc_ast2700_get_irq; } @@ -778,7 +778,7 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D { .name =3D "ast2700-a0", .parent =3D TYPE_ASPEED27X0_SOC, .instance_init =3D aspeed_soc_ast2700_init, - .class_init =3D aspeed_soc_ast2700_class_init, + .class_init =3D aspeed_soc_ast2700a0_class_init, }, }; =20 --=20 2.34.1 From nobody Sun Feb 8 20:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738835725726323.38327919071196; Thu, 6 Feb 2025 01:55:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfyZX-00023L-VI; Thu, 06 Feb 2025 04:53:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfyZR-000201-PT; Thu, 06 Feb 2025 04:53:18 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfyZQ-00051a-Bf; Thu, 06 Feb 2025 04:53:17 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Feb 2025 17:52:54 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Feb 2025 17:52:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 5/6] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Date: Thu, 6 Feb 2025 17:52:51 +0800 Message-ID: <20250206095253.928308-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250206095253.928308-1-jamin_lin@aspeedtech.com> References: <20250206095253.928308-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738835728196019000 Content-Type: text/plain; charset="utf-8" To improve readability, sort the IRQ table by IRQ number. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 50 ++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 39567fcab9..6a8487fee6 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -73,27 +73,13 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2700a0_irqmap[] =3D { - [ASPEED_DEV_UART0] =3D 132, - [ASPEED_DEV_UART1] =3D 132, - [ASPEED_DEV_UART2] =3D 132, - [ASPEED_DEV_UART3] =3D 132, - [ASPEED_DEV_UART4] =3D 8, - [ASPEED_DEV_UART5] =3D 132, - [ASPEED_DEV_UART6] =3D 132, - [ASPEED_DEV_UART7] =3D 132, - [ASPEED_DEV_UART8] =3D 132, - [ASPEED_DEV_UART9] =3D 132, - [ASPEED_DEV_UART10] =3D 132, - [ASPEED_DEV_UART11] =3D 132, - [ASPEED_DEV_UART12] =3D 132, - [ASPEED_DEV_FMC] =3D 131, [ASPEED_DEV_SDMC] =3D 0, - [ASPEED_DEV_SCU] =3D 12, - [ASPEED_DEV_ADC] =3D 130, + [ASPEED_DEV_HACE] =3D 4, [ASPEED_DEV_XDMA] =3D 5, - [ASPEED_DEV_EMMC] =3D 15, - [ASPEED_DEV_GPIO] =3D 130, + [ASPEED_DEV_UART4] =3D 8, + [ASPEED_DEV_SCU] =3D 12, [ASPEED_DEV_RTC] =3D 13, + [ASPEED_DEV_EMMC] =3D 15, [ASPEED_DEV_TIMER1] =3D 16, [ASPEED_DEV_TIMER2] =3D 17, [ASPEED_DEV_TIMER3] =3D 18, @@ -102,19 +88,33 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_TIMER6] =3D 21, [ASPEED_DEV_TIMER7] =3D 22, [ASPEED_DEV_TIMER8] =3D 23, - [ASPEED_DEV_WDT] =3D 131, - [ASPEED_DEV_PWM] =3D 131, + [ASPEED_DEV_DP] =3D 28, [ASPEED_DEV_LPC] =3D 128, [ASPEED_DEV_IBT] =3D 128, + [ASPEED_DEV_KCS] =3D 128, + [ASPEED_DEV_ADC] =3D 130, + [ASPEED_DEV_GPIO] =3D 130, [ASPEED_DEV_I2C] =3D 130, - [ASPEED_DEV_PECI] =3D 133, + [ASPEED_DEV_FMC] =3D 131, + [ASPEED_DEV_WDT] =3D 131, + [ASPEED_DEV_PWM] =3D 131, + [ASPEED_DEV_I3C] =3D 131, + [ASPEED_DEV_UART0] =3D 132, + [ASPEED_DEV_UART1] =3D 132, + [ASPEED_DEV_UART2] =3D 132, + [ASPEED_DEV_UART3] =3D 132, + [ASPEED_DEV_UART5] =3D 132, + [ASPEED_DEV_UART6] =3D 132, + [ASPEED_DEV_UART7] =3D 132, + [ASPEED_DEV_UART8] =3D 132, + [ASPEED_DEV_UART9] =3D 132, + [ASPEED_DEV_UART10] =3D 132, + [ASPEED_DEV_UART11] =3D 132, + [ASPEED_DEV_UART12] =3D 132, [ASPEED_DEV_ETH1] =3D 132, [ASPEED_DEV_ETH2] =3D 132, [ASPEED_DEV_ETH3] =3D 132, - [ASPEED_DEV_HACE] =3D 4, - [ASPEED_DEV_KCS] =3D 128, - [ASPEED_DEV_DP] =3D 28, - [ASPEED_DEV_I3C] =3D 131, + [ASPEED_DEV_PECI] =3D 133, [ASPEED_DEV_SDHCI] =3D 133, }; =20 --=20 2.34.1 From nobody Sun Feb 8 20:02:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1738835654; cv=none; d=zohomail.com; s=zohoarc; b=QjDsY1wNUPRe+9CxEMwudpVQFSqWZ3OKpEVo1+bFqT6BwW61PtJywtsvebgvrRzY/JP+CcXE7uiIXr4/2aSK9NJqxUWVSOI02AdgoZFMfArRV+XBNfZ9ld68LEN1lKBSMwri8j2Jx7W5d8gcuFQ+mElS2U+WapkWFwRZkRuMY9Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738835654; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=X+gf9YETT0B6QSDyhb27iDPv7k09ZFq53wLlpFZ0y/s=; b=G4r0Xs2sG4LaL/w7TL6szLkdHdbaA3Nt7EDEYFjGmrWTR4s/BLs9P/YKT9jjn0HA6EXE7PPqcUyis45gY7XEmQSw0QR6coVQLKnTilORTGq2fjJkpinTM7UkATOn39JgQsBF1JSQdxoxbv9IjVaReOCteklXj4gedpaQy6ffiGs= ARC-Authentication-Results: i=1; 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Thu, 6 Feb 2025 17:52:54 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Feb 2025 17:52:54 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 6/6] hw/intc/aspeed: Support different memory region ops Date: Thu, 6 Feb 2025 17:52:52 +0800 Message-ID: <20250206095253.928308-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250206095253.928308-1-jamin_lin@aspeedtech.com> References: <20250206095253.928308-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738835656041019000 Content-Type: text/plain; charset="utf-8" The previous implementation set the "aspeed_intc_ops" struct, containing re= ad and write callbacks, to be used when I/O is performed on the INTC region. Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used for INTC (CPU Die). To support the INTC_IO (IO Die) model, introduces a new "reg_ops" class attribute. This allows setting different memory region operations to support different INTC models. Will introduce "aspeed_intc_io_read" and "aspeed_intc_io_write" callback functions are used for INTC_IO. Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 5 ++++- include/hw/intc/aspeed_intc.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index e1e4a9fe59..e0e843201a 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -335,7 +335,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error= **errp) =20 sysbus_init_mmio(sbd, &s->iomem_container); =20 - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, + memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s, TYPE_ASPEED_INTC ".regs", aic->reg_size); =20 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); @@ -353,11 +353,14 @@ static void aspeed_intc_realize(DeviceState *dev, Err= or **errp) static void aspeed_intc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); =20 dc->desc =3D "ASPEED INTC Controller"; dc->realize =3D aspeed_intc_realize; device_class_set_legacy_reset(dc, aspeed_intc_reset); dc->vmsd =3D NULL; + + aic->reg_ops =3D &aspeed_intc_ops; } =20 static const TypeInfo aspeed_intc_info =3D { diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index ecaeb15aea..749d7c55be 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -43,6 +43,7 @@ struct AspeedINTCClass { uint32_t num_ints; uint64_t mem_size; uint64_t reg_size; + const MemoryRegionOps *reg_ops; }; =20 #endif /* ASPEED_INTC_H */ --=20 2.34.1