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Wed, 05 Feb 2025 17:31:31 -0800 (PST) Date: Wed, 5 Feb 2025 17:31:01 -0800 In-Reply-To: <20250206013105.3228344-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20250206013105.3228344-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.48.1.362.g079036d154-goog Message-ID: <20250206013105.3228344-14-wuhaotsh@google.com> Subject: [PATCH v3 13/17] hw/misc: Support NPCM8XX CLK Module Registers From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, chli30@nuvoton.corp-partner.google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=38xCkZwgKCuggeRKYdcRQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1738805749037019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM8XX adds a few new registers and have a different set of reset values to the CLK modules. This patch supports them. This patch doesn't support the new clock values generated by these registers. Currently no modules use these new clock values so they are not necessary at this point. Implementation of these clocks might be required when implementing these modules. Reviewed-by: Titus Rwantare Reviewed-by: Peter Maydell Signed-off-by: Hao Wu --- hw/misc/npcm_clk.c | 113 ++++++++++++++++++++++++++++++++++++- include/hw/misc/npcm_clk.h | 10 +++- 2 files changed, 120 insertions(+), 3 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 9ad66ce212..2ba3ac27c7 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx Clock Control Registers. + * Nuvoton NPCM7xx/8xx Clock Control Registers. * * Copyright 2020 Google LLC * @@ -75,6 +75,58 @@ enum NPCM7xxCLKRegisters { NPCM7XX_CLK_REGS_END, }; =20 +enum NPCM8xxCLKRegisters { + NPCM8XX_CLK_CLKEN1, + NPCM8XX_CLK_CLKSEL, + NPCM8XX_CLK_CLKDIV1, + NPCM8XX_CLK_PLLCON0, + NPCM8XX_CLK_PLLCON1, + NPCM8XX_CLK_SWRSTR, + NPCM8XX_CLK_IPSRST1 =3D 0x20 / sizeof(uint32_t), + NPCM8XX_CLK_IPSRST2, + NPCM8XX_CLK_CLKEN2, + NPCM8XX_CLK_CLKDIV2, + NPCM8XX_CLK_CLKEN3, + NPCM8XX_CLK_IPSRST3, + NPCM8XX_CLK_WD0RCR, + NPCM8XX_CLK_WD1RCR, + NPCM8XX_CLK_WD2RCR, + NPCM8XX_CLK_SWRSTC1, + NPCM8XX_CLK_SWRSTC2, + NPCM8XX_CLK_SWRSTC3, + NPCM8XX_CLK_TIPRSTC, + NPCM8XX_CLK_PLLCON2, + NPCM8XX_CLK_CLKDIV3, + NPCM8XX_CLK_CORSTC, + NPCM8XX_CLK_PLLCONG, + NPCM8XX_CLK_AHBCKFI, + NPCM8XX_CLK_SECCNT, + NPCM8XX_CLK_CNTR25M, + /* Registers unique to NPCM8XX SoC */ + NPCM8XX_CLK_CLKEN4, + NPCM8XX_CLK_IPSRST4, + NPCM8XX_CLK_BUSTO, + NPCM8XX_CLK_CLKDIV4, + NPCM8XX_CLK_WD0RCRB, + NPCM8XX_CLK_WD1RCRB, + NPCM8XX_CLK_WD2RCRB, + NPCM8XX_CLK_SWRSTC1B, + NPCM8XX_CLK_SWRSTC2B, + NPCM8XX_CLK_SWRSTC3B, + NPCM8XX_CLK_TIPRSTCB, + NPCM8XX_CLK_CORSTCB, + NPCM8XX_CLK_IPSRSTDIS1, + NPCM8XX_CLK_IPSRSTDIS2, + NPCM8XX_CLK_IPSRSTDIS3, + NPCM8XX_CLK_IPSRSTDIS4, + NPCM8XX_CLK_CLKENDIS1, + NPCM8XX_CLK_CLKENDIS2, + NPCM8XX_CLK_CLKENDIS3, + NPCM8XX_CLK_CLKENDIS4, + NPCM8XX_CLK_THRTL_CNT, + NPCM8XX_CLK_REGS_END, +}; + /* * These reset values were taken from version 0.91 of the NPCM750R data sh= eet. * @@ -103,6 +155,46 @@ static const uint32_t npcm7xx_cold_reset_values[NPCM7X= X_CLK_NR_REGS] =3D { [NPCM7XX_CLK_AHBCKFI] =3D 0x000000c8, }; =20 +/* + * These reset values were taken from version 0.92 of the NPCM8xx data she= et. + */ +static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_CLK_NR_REGS] =3D { + [NPCM8XX_CLK_CLKEN1] =3D 0xffffffff, + [NPCM8XX_CLK_CLKSEL] =3D 0x154aaaaa, + [NPCM8XX_CLK_CLKDIV1] =3D 0x5413f855, + [NPCM8XX_CLK_PLLCON0] =3D 0x00222101 | PLLCON_LOKI, + [NPCM8XX_CLK_PLLCON1] =3D 0x00202101 | PLLCON_LOKI, + [NPCM8XX_CLK_IPSRST1] =3D 0x00001000, + [NPCM8XX_CLK_IPSRST2] =3D 0x80000000, + [NPCM8XX_CLK_CLKEN2] =3D 0xffffffff, + [NPCM8XX_CLK_CLKDIV2] =3D 0xaa4f8f9f, + [NPCM8XX_CLK_CLKEN3] =3D 0xffffffff, + [NPCM8XX_CLK_IPSRST3] =3D 0x03000000, + [NPCM8XX_CLK_WD0RCR] =3D 0xffffffff, + [NPCM8XX_CLK_WD1RCR] =3D 0xffffffff, + [NPCM8XX_CLK_WD2RCR] =3D 0xffffffff, + [NPCM8XX_CLK_SWRSTC1] =3D 0x00000003, + [NPCM8XX_CLK_SWRSTC2] =3D 0x00000001, + [NPCM8XX_CLK_SWRSTC3] =3D 0x00000001, + [NPCM8XX_CLK_TIPRSTC] =3D 0x00000001, + [NPCM8XX_CLK_PLLCON2] =3D 0x00c02105 | PLLCON_LOKI, + [NPCM8XX_CLK_CLKDIV3] =3D 0x00009100, + [NPCM8XX_CLK_CORSTC] =3D 0x04000003, + [NPCM8XX_CLK_PLLCONG] =3D 0x01228606 | PLLCON_LOKI, + [NPCM8XX_CLK_AHBCKFI] =3D 0x000000c8, + [NPCM8XX_CLK_CLKEN4] =3D 0xffffffff, + [NPCM8XX_CLK_CLKDIV4] =3D 0x70009000, + [NPCM8XX_CLK_IPSRST4] =3D 0x02000000, + [NPCM8XX_CLK_WD0RCRB] =3D 0xfffffe71, + [NPCM8XX_CLK_WD1RCRB] =3D 0xfffffe71, + [NPCM8XX_CLK_WD2RCRB] =3D 0xfffffe71, + [NPCM8XX_CLK_SWRSTC1B] =3D 0xfffffe71, + [NPCM8XX_CLK_SWRSTC2B] =3D 0xfffffe71, + [NPCM8XX_CLK_SWRSTC3B] =3D 0xfffffe71, + [NPCM8XX_CLK_TIPRSTCB] =3D 0xfffffe71, + [NPCM8XX_CLK_CORSTCB] =3D 0xfffffe71, +}; + /* The number of watchdogs that can trigger a reset. */ #define NPCM7XX_NR_WATCHDOGS (3) =20 @@ -1058,6 +1150,18 @@ static void npcm7xx_clk_class_init(ObjectClass *klas= s, void *data) c->cold_reset_values =3D npcm7xx_cold_reset_values; } =20 +static void npcm8xx_clk_class_init(ObjectClass *klass, void *data) +{ + NPCMCLKClass *c =3D NPCM_CLK_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + QEMU_BUILD_BUG_ON(NPCM8XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS); + QEMU_BUILD_BUG_ON(NPCM8XX_CLK_REGS_END !=3D NPCM8XX_CLK_NR_REGS); + dc->desc =3D "NPCM8xx Clock Control Registers"; + c->nr_regs =3D NPCM8XX_CLK_NR_REGS; + c->cold_reset_values =3D npcm8xx_cold_reset_values; +} + static const TypeInfo npcm7xx_clk_pll_info =3D { .name =3D TYPE_NPCM7XX_CLOCK_PLL, .parent =3D TYPE_DEVICE, @@ -1098,6 +1202,12 @@ static const TypeInfo npcm7xx_clk_info =3D { .class_init =3D npcm7xx_clk_class_init, }; =20 +static const TypeInfo npcm8xx_clk_info =3D { + .name =3D TYPE_NPCM8XX_CLK, + .parent =3D TYPE_NPCM_CLK, + .class_init =3D npcm8xx_clk_class_init, +}; + static void npcm7xx_clk_register_type(void) { type_register_static(&npcm7xx_clk_pll_info); @@ -1105,5 +1215,6 @@ static void npcm7xx_clk_register_type(void) type_register_static(&npcm7xx_clk_divider_info); type_register_static(&npcm_clk_info); type_register_static(&npcm7xx_clk_info); + type_register_static(&npcm8xx_clk_info); } type_init(npcm7xx_clk_register_type); diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index f47614ac8d..8fa1e14bdd 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx Clock Control Registers. + * Nuvoton NPCM7xx/8xx Clock Control Registers. * * Copyright 2020 Google LLC * @@ -21,11 +21,12 @@ #include "hw/sysbus.h" =20 #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) +#define NPCM8XX_CLK_NR_REGS (0xc4 / sizeof(uint32_t)) /* * Number of maximum registers in NPCM device state structure. Don't change * this without incrementing the version_id in the vmstate. */ -#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS +#define NPCM_CLK_MAX_NR_REGS NPCM8XX_CLK_NR_REGS =20 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" =20 @@ -162,6 +163,10 @@ struct NPCMCLKState { MemoryRegion iomem; =20 /* Clock converters */ + /* + * TODO: Implement unique clock converters for NPCM8xx. + * NPCM8xx adds a few more clock outputs. + */ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; @@ -185,5 +190,6 @@ typedef struct NPCMCLKClass { #define TYPE_NPCM_CLK "npcm-clk" OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" +#define TYPE_NPCM8XX_CLK "npcm8xx-clk" =20 #endif /* NPCM_CLK_H */ --=20 2.48.1.362.g079036d154-goog