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From: Rajnesh Kanwal <rkanwal@rivosinc.com>
To: qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com,
beeman@rivosinc.com, jason.chien@sifive.com, frank.chang@sifive.com,
richard.henderson@linaro.org, bmeng.cn@gmail.com
Subject: [PATCH v6 5/7] target/riscv: Add CTR sctrclr instruction.
Date: Wed, 5 Feb 2025 11:18:49 +0000
Message-Id: <20250205-b4-ctr_upstream_v6-v6-5-439d8e06c8ef@rivosinc.com>
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X-ZM-MESSAGEID: 1738754488072019000
CTR extension adds a new instruction sctrclr to quickly
clear the recorded entries buffer.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 7 +++++++
target/riscv/helper.h | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_privileged.c.inc | 11 ++++++++++
target/riscv/op_helper.c | 29 ++++++++++++++++++++++=
++++
6 files changed, 50 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2d8212e2fefe21defb4ca007d894f02592ed3c89..88d47f6b4f19efe74afa51bdd14=
94706ac382b7b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -618,6 +618,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon=
g newpriv, bool virt_en);
=20
void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long =
dst,
enum CTRType type, target_ulong prev_priv, bool prev_virt);
+void riscv_ctr_clear(CPURISCVState *env);
=20
void riscv_translate_init(void);
void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index afecc822ae7d07a0904f1ec8c223845bbac92523..6225d42a5688f84eb2229a852f3=
4f4a89b0de9fa 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -887,6 +887,13 @@ static void riscv_ctr_freeze(CPURISCVState *env, uint6=
4_t freeze_mask,
}
}
=20
+void riscv_ctr_clear(CPURISCVState *env)
+{
+ memset(env->ctr_src, 0x0, sizeof(env->ctr_src));
+ memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst));
+ memset(env->ctr_data, 0x0, sizeof(env->ctr_data));
+}
+
static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
{
switch (priv) {
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 163121ade599f5ec2682ecea25a59b664593fba3..85d73e492d77f839613ecb6dd73=
cf1ec2a8f1567 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -132,6 +132,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
DEF_HELPER_1(sret, tl, env)
DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(mnret, tl, env)
+DEF_HELPER_1(ctr_clear, void, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(wrs_nto, void, env)
DEF_HELPER_1(tlb_flush, void, env)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a98dab02057648d9dae28eaf9f9ddb00079211e2..6d1a13c82603e47b7c515338988=
8ceffd13773c9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -114,6 +114,7 @@
# *** Privileged Instructions ***
ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
+sctrclr 000100000100 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/=
insn_trans/trans_privileged.c.inc
index ca52405d7da411907f1d52234df955940efdc25d..8a62b4cfcd9f9859bc24fbe4594=
e79d066df5df8 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -75,6 +75,17 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *=
a)
return true;
}
=20
+static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+ gen_helper_ctr_clear(tcg_env);
+ return true;
+ }
+#endif
+ return false;
+}
+
static bool trans_uret(DisasContext *ctx, arg_uret *a)
{
return false;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 5a99c47b128caf847df76cd1b534f9fdf15a28a8..f156bfab12da6cb4c1e55a4e945=
92c1d2d0e0e7c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -485,6 +485,35 @@ void helper_ctr_add_entry(CPURISCVState *env, target_u=
long src,
env->priv, env->virt_enabled);
}
=20
+void helper_ctr_clear(CPURISCVState *env)
+{
+ /*
+ * It's safe to call smstateen_acc_ok() for umode access regardless of=
the
+ * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the=
bit
+ * is zero, smstateen_acc_ok() will return the correct exception code =
and
+ * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that
+ * scenario the U-mode check below will handle that case.
+ */
+ RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
+ if (ret !=3D RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ if (env->priv =3D=3D PRV_U) {
+ /*
+ * One corner case is when sctrclr is executed from VU-mode and
+ * mstateen.CTR =3D 0, in which case we are supposed to raise
+ * RISCV_EXCP_ILLEGAL_INST. This case is already handled in
+ * smstateen_acc_ok().
+ */
+ uint32_t excep =3D env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION=
_FAULT :
+ RISCV_EXCP_ILLEGAL_INST;
+ riscv_raise_exception(env, excep, GETPC());
+ }
+
+ riscv_ctr_clear(env);
+}
+
void helper_wfi(CPURISCVState *env)
{
CPUState *cs =3D env_cpu(env);
--=20
2.34.1