From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738660911; cv=none; d=zohomail.com; s=zohoarc; b=CRFPlpHcQFSo4hIP0d8mlCyL4wbDFxmufVM3NQD8oaDDptGb99rzfsDSlzlcuqKSi2Iz54bnU60PjJ3Fl3LAu5x3jc7SzT9HBsS5pSylOiEe4ipDnaSuErNklAUEpssJRYCnLpiOJjVkaRCzsn0FtqR2k5GsDyNsX2ztPOfL46I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738660911; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=taPzlqnqNA89HRzJHV1fOaa3mxJcu/UNcmQ7477fRUY=; b=g0IXQp/6sKdgiiz8qK+tTl6FCbVYEYys6sXb8JrphEZSpe7kdoIaBaJetngCBuzkEaw+M24nRSAud5EdqoCClHqhSRI8H4jY4dM/LFZ+iNv4Z9hLoI+OJ0x/Xt5j8qBMc42UZckfzpkMUgHASjAfK0Oo/FdLGI/Y6R+bUYKyKpY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173866091151955.53176313330687; Tue, 4 Feb 2025 01:21:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF7Y-0004i7-M4; Tue, 04 Feb 2025 04:21:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7W-0004gc-F1; Tue, 04 Feb 2025 04:21:26 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7U-00052H-HC; Tue, 04 Feb 2025 04:21:26 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-385df53e559so3851069f8f.3; Tue, 04 Feb 2025 01:21:23 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. [2003:fa:af00:4300:6a2c:ae69:f03f:1c85]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23d42c7sm187233595e9.3.2025.02.04.01.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 01:21:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738660881; x=1739265681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=taPzlqnqNA89HRzJHV1fOaa3mxJcu/UNcmQ7477fRUY=; b=gyH3oW3LVOkZ7Z7tG1A+R+IGU/tvJhGsij7tOAXTidkAMFgr/susG3mvnuN8H3oI/i gbYcucb5r/Nc9Lv20EePAsJlnQGwAbCU4AhZmHwIs0g8WWOTOYywvU0ffcNxnQohk24w vRiL6Z/GUMb/wiTrF4Q8vR7+o4c6ziFoi7e/vTRNPcKA6jCVblobVHn2cSKeu2JryhFw NDe/UtIw8O2RmhzMLw7836EnUh74pPqGJ9H9fEEZnXDkrk/toDbQKb4QrmYDql7tW1CP uTQddX0Pb1FAe1fL3WLgvEZUIMYCQj5UIn3xYV3LgOnKDbauAz0v1EAlc4GZ73DbbahM n0Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738660881; x=1739265681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=taPzlqnqNA89HRzJHV1fOaa3mxJcu/UNcmQ7477fRUY=; b=G9GkOhU+wh4qI1D9rbXKqBpdwFB59eeE+itJB5qs8Cb1bSUgEN8qgQeU0xMGvZ2VLv +SW2yO87Y1708RT9TnkVXf021sjHXRCHz2M8XoLwOvRRfFEXm/Ix/M+bfZhqbScfW4wL IEiLRxHJA4HyKlD7+zleIA+GhVuDK5aNOxXKGp12sR9tNMPuMOQ56qaaEXqRKZjawd1V Pm5oRioAePqJSphWa2bJPGIqHBIDwj6gyNfgXzH1tQoA5wCBGu8OC0iiXzrNs3Wqpe5w rXR6csy404QZP1B6UsyFHn0Ec8gQYNhplK2L9KeT4H1J4d8YR80I2D2ny3XYztF/yUrH d7bg== X-Forwarded-Encrypted: i=1; AJvYcCXRyJ2o65F2RaVdrICgqxavGHZR6qvKWLhKPNzm8kjITz8Npu/nIza4Fxsrh/o/DK19Jx/843H1rQ==@nongnu.org X-Gm-Message-State: AOJu0Yz4JyWOMLHCkOsqHnddHLoJDFqtx/ZliqSkDEhGDAEX3mj+jBJg y/MUdrW0QDHBN+HLWZ0V/QhtZbmH02JOj/C9TAUAYZwzEN0xdT6cFjLraQ== X-Gm-Gg: ASbGncvU580/j0aRXiYwpMV8EEiFV+iutQkVOMCeYm//1vIRUJ0VNBZ+ogxBAaP+Rlw zUNYRI5T4qjIMAjneflD7jN4otTVsVXA3wILydnhCDqSqVanwPSWp0GFUskPL2wCyomjSF4PGyK EzFtOGK7xmpYroSjSyX0lo1e87l3fjy8Xf50J9DRU0DpbNU7OqftGZ7zICct9B0uuYtGvUEcURS ajyv3JrDxpEQBI+7I0H01bli4iRg6YW6iAcCqLXa1iSh5IfaeilA/45GHpCnA+Qyvbnkk6gaHyr huw7fI+FzbZpdhzq1jEV/K/zQ6dV1nIjxfbx2igmJYpkMIREVNW4aTZqW0YuC+xHNhdhj7eIzIq blQGfWth0Bw== X-Google-Smtp-Source: AGHT+IFyW+/j5oudqjddyIlU0MbrBUA6x+bFQO0Dn3j6+5R9SMUEPfMe4pq837BpZgajE2TWvp1NGw== X-Received: by 2002:adf:ee8b:0:b0:382:3c7b:9ae with SMTP id ffacd0b85a97d-38c51943ddemr18272968f8f.16.1738660881343; Tue, 04 Feb 2025 01:21:21 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 01/18] hw/usb/hcd-dwc3: Align global registers size with Linux Date: Tue, 4 Feb 2025 10:20:55 +0100 Message-ID: <20250204092112.26957-2-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=shentey@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738660913265019100 Content-Type: text/plain; charset="utf-8" While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus refer= ence manual. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- include/hw/usb/hcd-dwc3.h | 2 +- hw/usb/hcd-dwc3.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h index f752a27e94..dbdf12b21d 100644 --- a/include/hw/usb/hcd-dwc3.h +++ b/include/hw/usb/hcd-dwc3.h @@ -35,7 +35,7 @@ #define USB_DWC3(obj) \ OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3) =20 -#define USB_DWC3_R_MAX ((0x530 / 4) + 1) +#define USB_DWC3_R_MAX (0x600 / 4) #define DWC3_SIZE 0x10000 =20 typedef struct USBDWC3 { diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c index 9ce9ba0b04..0bceee2712 100644 --- a/hw/usb/hcd-dwc3.c +++ b/hw/usb/hcd-dwc3.c @@ -343,6 +343,8 @@ REG32(GFLADJ, 0x530) FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14) FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1) FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6) +REG32(GUSB2RHBCTL, 0x540) + FIELD(GUSB2RHBCTL, OVRD_L1TIMEOUT, 0, 4) =20 #define DWC3_GLOBAL_OFFSET 0xC100 static void reset_csr(USBDWC3 * s) @@ -560,6 +562,9 @@ static const RegisterAccessInfo usb_dwc3_regs_info[] = =3D { .rsvd =3D 0x40, .ro =3D 0x400040, .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2RHBCTL", .addr =3D A_GUSB2RHBCTL, + .rsvd =3D 0xfffffff0, + .unimp =3D 0xffffffff, } }; =20 --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738660980; cv=none; d=zohomail.com; s=zohoarc; b=ln7kixcOZ6cQWKTSUvJIvh1QIQ2+xGiq9JjtJuzAkxA+yNu0wW0pIiCMHdtHYzeIWarKg08LXXu93bvtrP1ix8Pz+JdjTYtPEgBivFMV6IhCy7q3lcVquStmcgsdwMDP9rcbl/4ryeQ7B6e0D/oRn/DLzAfFV+1pUzMDXllf1hA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738660980; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r8qJcnNvkV2vDa+pvhn/pUMBPEEUiO9U4AbL5C/A4EI=; b=LqSGbzcufDtmvwVJG0LL8ueFaGKsxT7iJLOMKyI8pEjS6w7rPwXvfH0MMtOpbOuPvJmSCV09sfmolR0bMgYv3VPia3k6ec9B//c58cHCXOxJfXkaxCT4pSg+uBCexDWvMczmIyOaxt/ru+MatkCEdeH3QQGqh8sno1TN4b5t2Ro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738660980432194.57677193387087; Tue, 4 Feb 2025 01:23:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF7Y-0004iF-RO; Tue, 04 Feb 2025 04:21:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7X-0004hI-SQ; Tue, 04 Feb 2025 04:21:27 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7V-00052V-UP; Tue, 04 Feb 2025 04:21:27 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-436281c8a38so37592785e9.3; Tue, 04 Feb 2025 01:21:25 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. [2003:fa:af00:4300:6a2c:ae69:f03f:1c85]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23d42c7sm187233595e9.3.2025.02.04.01.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 01:21:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738660883; x=1739265683; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r8qJcnNvkV2vDa+pvhn/pUMBPEEUiO9U4AbL5C/A4EI=; b=M/v57iB4Kjy7a8+3loZLfcT00Fq8ANfbbvNuDKCybpKTRYdgudvNppThI88fJSybDE jZZfN0APomYCews0TCB5OF/7eaP7VIrGuGXETU8qAfSzJKtXZq6VI7GLwDeUSi1JtJu7 it2Hr6SPU6UkbMIj2SY6K7bn0OQc3ByTtxErvQQp9Ch/5NohFOZ9PXk4rZYZEr+qxaKW Xg6SOqwbJcQRnSF9EwaKifWceZgBlG5jKvhgsjl4B35inLJ7jTyMxFvb1LPq3Y1alI+h ZckqR94S/sVpBcmU8XCjpjHzEFhGNI7g2hpbjPdnKw3xVxuwA1zAknTVZnPcnOjd0VlZ Utgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738660883; x=1739265683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8qJcnNvkV2vDa+pvhn/pUMBPEEUiO9U4AbL5C/A4EI=; b=qRQIDMlWPTjD98BvryGS52t7yXOwZQr0oZl34TfMb1F7z8LdLlik8aN1qepquVCHIv R6vLdgR6AnlA9b6E465V+5AJ2hqWTWcxKaT6j+JusSzRZhz5Rf2m3RaTWP6idmWY+h8d sT4TpY9wuOSSbOSS+oqItCAt2UH04eTJFjAhGhOv/2DtSoDxgRdToVZy3pYxa52fPBqk 0YHcYImI2is/K09m807C3r07fItFx/zoblPj1F5m6XK8jqxaPkcuvV//i7Z5OouFn45w KVicke4WP8G2vNTB6VEURaLmICK7BqfFNO1N09+7WcDl2kT/oha7osmQBCAZtGn+S4/2 A8AQ== X-Forwarded-Encrypted: i=1; AJvYcCV7xDphUFhkCYFlznmclSN/ycjp1tf3PL7LO8DSx9GV7dpjsb5BdEZ+ODolKc7ycS54wIsHCBXZdQ==@nongnu.org X-Gm-Message-State: AOJu0YxU6PDa1bh+ZwUZQubL1fj1fPs1/ogNHqyFGWzvxNHuM+xxnQdA vXN6qZRJHDcKDWEGxVg96s5s7toXe8Tlpv06lEDgaxRdOIcF0Ivmx2InJg== X-Gm-Gg: ASbGnctc8j8HHMgSKra8FCugFYbrAgI54nLq2wX35McPsDO1secsspp3g7bEGLPyofL vhEccAxRqGePQuYQlwhZdl2ri3Gk5M4MVw3k+IJ6akPYb1lKqs7OWVvMVkwc0uSVgpQq0iYgO4J vQ/Vb32mr8lHFRbw9jRJjn3WNwtW4o88voP+zEJje54qp4tOVdpmoGwS9gK2bcDoZl3lp7Q7ULp VeOMh8k8ItKXT2lUsyKHNAdWHZ3xyzVQSqR0iqFrwcpFGQHc4uJMSjLFBZX5wMJHoe7hKZZS1t+ XkhrsVBYLSKtumj/YaEw48sjMpHWyLt14nSDjeczHm1jdlyQMbjKef8dWjVLGXAWI6OQZcinmF2 h3YEvJgwXmw== X-Google-Smtp-Source: AGHT+IGFnzhzFoa5lrzn5Br0tkTkWOKQ8AYyqJR7VRaIeZ6WJVyhVa8hl93unPjbRIxst2+Da+7BEw== X-Received: by 2002:a05:600c:4c24:b0:434:f609:1afa with SMTP id 5b1f17b1804b1-438e01fdfe1mr191296755e9.4.1738660883217; Tue, 04 Feb 2025 01:21:23 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 02/18] hw/pci-host/designware: Prevent device attachment on internal PCIe root bus Date: Tue, 4 Feb 2025 10:20:56 +0100 Message-ID: <20250204092112.26957-3-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=shentey@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738660981563019100 Content-Type: text/plain; charset="utf-8" On the real device, the PCIe root bus is only connected to a PCIe bridge and does not allow for direct attachment of devices. Doing so in QEMU results i= n no PCI devices being detected by Linux. Instead, PCI devices should plug into = the secondary PCIe bus spawned by the internal PCIe bridge. Unfortunately, QEMU defaults to plugging devices into the PCIe root bus. To= work around this, every PCI device created on the command line needs an extra `bus=3Ddw-pcie` option which is error prone. Fix that by marking the PCIe r= oot bus as full which makes QEMU decend into the child PCIe bus. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- include/hw/pci-host/designware.h | 7 +++++++ hw/pci-host/designware.c | 18 +++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designw= are.h index bf8b278978..a35a3bd06c 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -25,12 +25,19 @@ #include "hw/pci/pci_bridge.h" #include "qom/object.h" =20 +#define TYPE_DESIGNWARE_PCIE_ROOT_BUS "designware-pcie-root-BUS" +OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERootBus, DESIGNWARE_PCIE_ROOT_BUS) + #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host" OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST) =20 #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root" OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT) =20 +struct DesignwarePCIERootBus { + PCIBus parent; +}; + typedef struct DesignwarePCIEViewport { DesignwarePCIERoot *root; =20 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 3e8c36e6a7..c07740bfaa 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -55,6 +55,17 @@ #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C =20 +static void designware_pcie_root_bus_class_init(ObjectClass *klass, void *= data) +{ + BusClass *k =3D BUS_CLASS(klass); + + /* + * Designware has only a single root complex. Enforce the limit on the + * parent bus + */ + k->max_dev =3D 1; +} + static DesignwarePCIEHost * designware_pcie_root_to_host(DesignwarePCIERoot *root) { @@ -699,7 +710,7 @@ static void designware_pcie_host_realize(DeviceState *d= ev, Error **errp) &s->pci.memory, &s->pci.io, 0, 4, - TYPE_PCIE_BUS); + TYPE_DESIGNWARE_PCIE_ROOT_BUS); pci->bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE; =20 memory_region_init(&s->pci.address_space_root, @@ -754,6 +765,11 @@ static void designware_pcie_host_init(Object *obj) =20 static const TypeInfo designware_pcie_types[] =3D { { + .name =3D TYPE_DESIGNWARE_PCIE_ROOT_BUS, + .parent =3D TYPE_PCIE_BUS, + .instance_size =3D sizeof(DesignwarePCIERootBus), + .class_init =3D designware_pcie_root_bus_class_init, + }, { .name =3D TYPE_DESIGNWARE_PCIE_HOST, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(DesignwarePCIEHost), --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738660902; cv=none; d=zohomail.com; s=zohoarc; b=O6LMB4ikTbdZMvwzUzcgWZcd+mC36pgoltqhShHA1zb29/PkuT9ATo8d2xo8wNsGRFCEZU9sJX5ET3joGqe8j1Z8OnPuCqrRix9hRz7L5qD82tT+YO/FoZevR7SlOKAr7enwyOxHbRP4kduLf2Ewce/ZbZFzzXWptOT9G5Gi0xI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738660902; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RWwFZAblT8IJuxVnOIUdY36BCPwzLgHd8Wv7Hgxbpe8=; b=jyeQLbKwjhRBxm23O0B8oGamev72P11K3dN3jNOWzeRah19MJhGCWghhFJr1O6UscYoQ8LXK9+GnIK6EI50DjJIAqU1T7/ArP/PSZXg9YlJJ719QsWAOQQPx04YNt+peCPrbarnlgtoVKX2MpSWy9c1JErzdRogxIITvHVrJZa4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738660902302293.29500624886714; Tue, 4 Feb 2025 01:21:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF7b-0004mT-Dj; Tue, 04 Feb 2025 04:21:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7Y-0004i6-JK; Tue, 04 Feb 2025 04:21:28 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7W-00052e-Qm; Tue, 04 Feb 2025 04:21:28 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-437a92d7b96so53131735e9.2; Tue, 04 Feb 2025 01:21:26 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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Signed-off-by: Bernhard Beschow --- hw/gpio/Kconfig | 10 ++++++++++ hw/misc/Kconfig | 8 -------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index c423e10f59..007048c688 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -16,6 +16,16 @@ config SIFIVE_GPIO config STM32L4X5_GPIO bool =20 +config PCA9552 + bool + depends on I2C + default y if I2C_DEVICES + +config PCA9554 + bool + depends on I2C + default y if I2C_DEVICES + config PCF8574 bool depends on I2C diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 8f9ce2f68c..4271e2f4ac 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -30,14 +30,6 @@ config EDU default y if TEST_DEVICES depends on PCI && MSI_NONBROKEN =20 -config PCA9552 - bool - depends on I2C - -config PCA9554 - bool - depends on I2C - config I2C_ECHO bool default y if TEST_DEVICES --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738661035; cv=none; d=zohomail.com; s=zohoarc; b=ZWf97JDg2rVeBjMo3q7mYAVRyVst5WM5EDGrLRqtRjMc9nXQk3ShzrTYo0nY3AMQ/fOZngdLJqDyoNPu+kKKo6rw+r+LE/d9THjnLwrMYP5YtYq94MzUeUmvh1in84GnqkBgI/GRAExQOn1koVjPtDZY927eSdFA6HGhsbCuOe8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738661035; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cWeGJV8lxpMyWqQ0ohwO6lTA2TIWenKMbVoNYi2bA2A=; b=RnfVTIUifj8Fx3FeZjSfgcD6Bcy9rUG6/qKRQmJaRGZPRwns7MHEgs0bTFgwFLvthz3wCYguNFm74H1kfEvcijOAS3zv9yXs22cm/cyYhAxuQoS7m3o7yS4r+XHiG/Fzed3PMuo6xVB7ksxqeHmeCVW5YQSPkoUduuzkD4wNY0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738661035079653.6512394543342; Tue, 4 Feb 2025 01:23:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF7e-0004nV-9j; Tue, 04 Feb 2025 04:21:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7c-0004mc-EG; Tue, 04 Feb 2025 04:21:32 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7Y-000538-Ur; Tue, 04 Feb 2025 04:21:32 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4361f664af5so61802305e9.1; Tue, 04 Feb 2025 01:21:27 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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All other devices of the A53 memory map are represented as TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allo= ws for running Linux without it crashing due to invalid memory accesses. Signed-off-by: Bernhard Beschow --- MAINTAINERS | 9 + docs/system/arm/imx8mp-evk.rst | 56 +++++ docs/system/target-arm.rst | 1 + include/hw/arm/fsl-imx8mp.h | 189 +++++++++++++++++ hw/arm/fsl-imx8mp.c | 371 +++++++++++++++++++++++++++++++++ hw/arm/imx8mp-evk.c | 55 +++++ hw/arm/Kconfig | 12 ++ hw/arm/meson.build | 2 + 8 files changed, 695 insertions(+) create mode 100644 docs/system/arm/imx8mp-evk.rst create mode 100644 include/hw/arm/fsl-imx8mp.h create mode 100644 hw/arm/fsl-imx8mp.c create mode 100644 hw/arm/imx8mp-evk.c diff --git a/MAINTAINERS b/MAINTAINERS index 0cf37fce7b..8db59114bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -820,6 +820,15 @@ F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h F: docs/system/arm/mcimx7d-sabre.rst =20 +MCIMX8MP-EVK / i.MX8MP +M: Bernhard Beschow +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/imx8mp-evk.c +F: hw/arm/fsl-imx8mp.c +F: include/hw/arm/fsl-imx8mp.h +F: docs/system/arm/imx8mp-evk.rst + MPS2 / MPS3 M: Peter Maydell L: qemu-arm@nongnu.org diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst new file mode 100644 index 0000000000..a9c1fab390 --- /dev/null +++ b/docs/system/arm/imx8mp-evk.rst @@ -0,0 +1,56 @@ +NXP i.MX 8M Plus Evaluation Kit (``imx8mp-evk``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The QEMU i.MX 8M Plus EVK board emulation is intended to emulate a plain i= .MX 8M +Plus system on chip (SoC). All peripherals the real board has such as flas= h and +I2C devices are intended to be added via configuration, e.g. command line. + +Supported devices +----------------- + +The ``imx8mp-evk`` machine implements the following devices: + + * Up to 4 Cortex-A53 Cores + * Generic Interrupt Controller (GICv3) + * 4 UARTs + +Boot options +------------ + +The ``imx8mp-evk`` machine can start using the standard -kernel functional= ity +for loading a Linux kernel. + +Direct Linux Kernel Boot +'''''''''''''''''''''''' + +Probably the easiest way to get started with a whole Linux system on the m= achine +is to generate an image with Buildroot. Version 2024.11.1 is tested at the= time +of writing and involves two steps. First run the following commands in the +toplevel directory of the Buildroot source tree: + +.. code-block:: bash + + $ echo "BR2_TARGET_ROOTFS_CPIO=3Dy" >> configs/freescale_imx8mpevk_defco= nfig + $ make freescale_imx8mpevk_defconfig + $ make + +Once finished successfully there is an ``output/image`` subfolder. Navigat= e into +it patch the device tree needs to be patched with the following commands w= hich +will remove the ``cpu-idle-states`` properties from CPU nodes: + +.. code-block:: bash + + $ dtc imx8mp-evk.dtb | sed '/cpu-idle-states/d' > imx8mp-evk-patched.dts + $ dtc imx8mp-evk-patched.dts -o imx8mp-evk-patched.dtb + +Now that everything is prepared the newly built image can be run in the QE= MU +``imx8mp-evk`` machine: + +.. code-block:: bash + + $ qemu-system-aarch64 -M imx8mp-evk -smp 4 -m 3G \ + -display none -serial null -serial stdio \ + -kernel Image \ + -dtb imx8mp-evk-patched.dtb \ + -initrd rootfs.cpio \ + -append "root=3D/dev/ram" diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 9aaa9c414c..a43ec8f10e 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -95,6 +95,7 @@ Board-specific documentation arm/imx25-pdk arm/mcimx6ul-evk arm/mcimx7d-sabre + arm/imx8mp-evk arm/orangepi arm/raspi arm/collie diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h new file mode 100644 index 0000000000..57e23d1b69 --- /dev/null +++ b/include/hw/arm/fsl-imx8mp.h @@ -0,0 +1,189 @@ +/* + * i.MX 8M Plus SoC Definitions + * + * Copyright (c) 2024, Bernhard Beschow + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef FSL_IMX8MP_H +#define FSL_IMX8MP_H + +#include "cpu.h" +#include "hw/char/imx_serial.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qom/object.h" +#include "qemu/units.h" + +#define TYPE_FSL_IMX8MP "fsl-imx8mp" +OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP) + +#define FSL_IMX8MP_RAM_START 0x40000000 +#define FSL_IMX8MP_RAM_SIZE_MAX (8 * GiB) + +enum FslImx8mpConfiguration { + FSL_IMX8MP_NUM_CPUS =3D 4, + FSL_IMX8MP_NUM_IRQS =3D 160, + FSL_IMX8MP_NUM_UARTS =3D 4, +}; + +struct FslImx8mpState { + DeviceState parent_obj; + + ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; + GICv3State gic; + IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; +}; + +enum FslImx8mpMemoryRegions { + FSL_IMX8MP_A53_DAP, + FSL_IMX8MP_AIPS1_CONFIGURATION, + FSL_IMX8MP_AIPS2_CONFIGURATION, + FSL_IMX8MP_AIPS3_CONFIGURATION, + FSL_IMX8MP_AIPS4_CONFIGURATION, + FSL_IMX8MP_AIPS5_CONFIGURATION, + FSL_IMX8MP_ANA_OSC, + FSL_IMX8MP_ANA_PLL, + FSL_IMX8MP_ANA_TSENSOR, + FSL_IMX8MP_APBH_DMA, + FSL_IMX8MP_ASRC, + FSL_IMX8MP_AUDIO_BLK_CTRL, + FSL_IMX8MP_AUDIO_DSP, + FSL_IMX8MP_AUDIO_XCVR_RX, + FSL_IMX8MP_AUD_IRQ_STEER, + FSL_IMX8MP_BOOT_ROM, + FSL_IMX8MP_BOOT_ROM_PROTECTED, + FSL_IMX8MP_CAAM, + FSL_IMX8MP_CAAM_MEM, + FSL_IMX8MP_CCM, + FSL_IMX8MP_CSU, + FSL_IMX8MP_DDR_BLK_CTRL, + FSL_IMX8MP_DDR_CTL, + FSL_IMX8MP_DDR_PERF_MON, + FSL_IMX8MP_DDR_PHY, + FSL_IMX8MP_DDR_PHY_BROADCAST, + FSL_IMX8MP_ECSPI1, + FSL_IMX8MP_ECSPI2, + FSL_IMX8MP_ECSPI3, + FSL_IMX8MP_EDMA_CHANNELS, + FSL_IMX8MP_EDMA_MANAGEMENT_PAGE, + FSL_IMX8MP_ENET1, + FSL_IMX8MP_ENET2_TSN, + FSL_IMX8MP_FLEXCAN1, + FSL_IMX8MP_FLEXCAN2, + FSL_IMX8MP_GIC_DIST, + FSL_IMX8MP_GIC_REDIST, + FSL_IMX8MP_GPC, + FSL_IMX8MP_GPIO1, + FSL_IMX8MP_GPIO2, + FSL_IMX8MP_GPIO3, + FSL_IMX8MP_GPIO4, + FSL_IMX8MP_GPIO5, + FSL_IMX8MP_GPT1, + FSL_IMX8MP_GPT2, + FSL_IMX8MP_GPT3, + FSL_IMX8MP_GPT4, + FSL_IMX8MP_GPT5, + FSL_IMX8MP_GPT6, + FSL_IMX8MP_GPU2D, + FSL_IMX8MP_GPU3D, + FSL_IMX8MP_HDMI_TX, + FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR, + FSL_IMX8MP_HSIO_BLK_CTL, + FSL_IMX8MP_I2C1, + FSL_IMX8MP_I2C2, + FSL_IMX8MP_I2C3, + FSL_IMX8MP_I2C4, + FSL_IMX8MP_I2C5, + FSL_IMX8MP_I2C6, + FSL_IMX8MP_INTERCONNECT, + FSL_IMX8MP_IOMUXC, + FSL_IMX8MP_IOMUXC_GPR, + FSL_IMX8MP_IPS_DEWARP, + FSL_IMX8MP_ISI, + FSL_IMX8MP_ISP1, + FSL_IMX8MP_ISP2, + FSL_IMX8MP_LCDIF1, + FSL_IMX8MP_LCDIF2, + FSL_IMX8MP_MEDIA_BLK_CTL, + FSL_IMX8MP_MIPI_CSI1, + FSL_IMX8MP_MIPI_CSI2, + FSL_IMX8MP_MIPI_DSI1, + FSL_IMX8MP_MU_1_A, + FSL_IMX8MP_MU_1_B, + FSL_IMX8MP_MU_2_A, + FSL_IMX8MP_MU_2_B, + FSL_IMX8MP_MU_3_A, + FSL_IMX8MP_MU_3_B, + FSL_IMX8MP_NPU, + FSL_IMX8MP_OCOTP_CTRL, + FSL_IMX8MP_OCRAM, + FSL_IMX8MP_OCRAM_S, + FSL_IMX8MP_PCIE1, + FSL_IMX8MP_PCIE1_MEM, + FSL_IMX8MP_PCIE_PHY1, + FSL_IMX8MP_PDM, + FSL_IMX8MP_PERFMON1, + FSL_IMX8MP_PERFMON2, + FSL_IMX8MP_PWM1, + FSL_IMX8MP_PWM2, + FSL_IMX8MP_PWM3, + FSL_IMX8MP_PWM4, + FSL_IMX8MP_QOSC, + FSL_IMX8MP_QSPI, + FSL_IMX8MP_QSPI1_RX_BUFFER, + FSL_IMX8MP_QSPI1_TX_BUFFER, + FSL_IMX8MP_QSPI_MEM, + FSL_IMX8MP_RAM, + FSL_IMX8MP_RDC, + FSL_IMX8MP_SAI1, + FSL_IMX8MP_SAI2, + FSL_IMX8MP_SAI3, + FSL_IMX8MP_SAI5, + FSL_IMX8MP_SAI6, + FSL_IMX8MP_SAI7, + FSL_IMX8MP_SDMA1, + FSL_IMX8MP_SDMA2, + FSL_IMX8MP_SDMA3, + FSL_IMX8MP_SEMAPHORE1, + FSL_IMX8MP_SEMAPHORE2, + FSL_IMX8MP_SEMAPHORE_HS, + FSL_IMX8MP_SNVS_HP, + FSL_IMX8MP_SPBA1, + FSL_IMX8MP_SPBA2, + FSL_IMX8MP_SRC, + FSL_IMX8MP_SYSCNT_CMP, + FSL_IMX8MP_SYSCNT_CTRL, + FSL_IMX8MP_SYSCNT_RD, + FSL_IMX8MP_TCM_DTCM, + FSL_IMX8MP_TCM_ITCM, + FSL_IMX8MP_TZASC, + FSL_IMX8MP_UART1, + FSL_IMX8MP_UART2, + FSL_IMX8MP_UART3, + FSL_IMX8MP_UART4, + FSL_IMX8MP_USB1, + FSL_IMX8MP_USB2, + FSL_IMX8MP_USDHC1, + FSL_IMX8MP_USDHC2, + FSL_IMX8MP_USDHC3, + FSL_IMX8MP_VPU, + FSL_IMX8MP_VPU_BLK_CTRL, + FSL_IMX8MP_VPU_G1_DECODER, + FSL_IMX8MP_VPU_G2_DECODER, + FSL_IMX8MP_VPU_VC8000E_ENCODER, + FSL_IMX8MP_WDOG1, + FSL_IMX8MP_WDOG2, + FSL_IMX8MP_WDOG3, +}; + +enum FslImx8mpIrqs { + FSL_IMX8MP_UART1_IRQ =3D 26, + FSL_IMX8MP_UART2_IRQ =3D 27, + FSL_IMX8MP_UART3_IRQ =3D 28, + FSL_IMX8MP_UART4_IRQ =3D 29, + FSL_IMX8MP_UART5_IRQ =3D 30, + FSL_IMX8MP_UART6_IRQ =3D 16, +}; + +#endif /* FSL_IMX8MP_H */ diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c new file mode 100644 index 0000000000..0836d82ca0 --- /dev/null +++ b/hw/arm/fsl-imx8mp.c @@ -0,0 +1,371 @@ +/* + * i.MX 8M Plus SoC Implementation + * + * Based on hw/arm/fsl-imx6.c + * + * Copyright (c) 2024, Bernhard Beschow + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "hw/arm/bsa.h" +#include "hw/arm/fsl-imx8mp.h" +#include "hw/intc/arm_gicv3.h" +#include "hw/misc/unimp.h" +#include "hw/boards.h" +#include "system/system.h" +#include "target/arm/cpu-qom.h" +#include "qapi/qmp/qlist.h" +#include "qapi/error.h" + +static const struct { + hwaddr addr; + size_t size; + const char *name; +} fsl_imx8mp_memmap[] =3D { + [FSL_IMX8MP_RAM] =3D { FSL_IMX8MP_RAM_START, FSL_IMX8MP_RAM_SIZE_MAX, = "ram" }, + [FSL_IMX8MP_DDR_PHY_BROADCAST] =3D { 0x3dc00000, 4 * MiB, "ddr_phy_bro= adcast" }, + [FSL_IMX8MP_DDR_PERF_MON] =3D { 0x3d800000, 4 * MiB, "ddr_perf_mon" }, + [FSL_IMX8MP_DDR_CTL] =3D { 0x3d400000, 4 * MiB, "ddr_ctl" }, + [FSL_IMX8MP_DDR_BLK_CTRL] =3D { 0x3d000000, 1 * MiB, "ddr_blk_ctrl" }, + [FSL_IMX8MP_DDR_PHY] =3D { 0x3c000000, 16 * MiB, "ddr_phy" }, + [FSL_IMX8MP_AUDIO_DSP] =3D { 0x3b000000, 16 * MiB, "audio_dsp" }, + [FSL_IMX8MP_GIC_DIST] =3D { 0x38800000, 512 * KiB, "gic_dist" }, + [FSL_IMX8MP_GIC_REDIST] =3D { 0x38880000, 512 * KiB, "gic_redist" }, + [FSL_IMX8MP_NPU] =3D { 0x38500000, 2 * MiB, "npu" }, + [FSL_IMX8MP_VPU] =3D { 0x38340000, 2 * MiB, "vpu" }, + [FSL_IMX8MP_VPU_BLK_CTRL] =3D { 0x38330000, 2 * MiB, "vpu_blk_ctrl" }, + [FSL_IMX8MP_VPU_VC8000E_ENCODER] =3D { 0x38320000, 2 * MiB, "vpu_vc800= 0e_encoder" }, + [FSL_IMX8MP_VPU_G2_DECODER] =3D { 0x38310000, 2 * MiB, "vpu_g2_decoder= " }, + [FSL_IMX8MP_VPU_G1_DECODER] =3D { 0x38300000, 2 * MiB, "vpu_g1_decoder= " }, + [FSL_IMX8MP_USB2] =3D { 0x38200000, 1 * MiB, "usb2" }, + [FSL_IMX8MP_USB1] =3D { 0x38100000, 1 * MiB, "usb1" }, + [FSL_IMX8MP_GPU2D] =3D { 0x38008000, 32 * KiB, "gpu2d" }, + [FSL_IMX8MP_GPU3D] =3D { 0x38000000, 32 * KiB, "gpu3d" }, + [FSL_IMX8MP_QSPI1_RX_BUFFER] =3D { 0x34000000, 32 * MiB, "qspi1_rx_buf= fer" }, + [FSL_IMX8MP_PCIE1] =3D { 0x33800000, 4 * MiB, "pcie1" }, + [FSL_IMX8MP_QSPI1_TX_BUFFER] =3D { 0x33008000, 32 * KiB, "qspi1_tx_buf= fer" }, + [FSL_IMX8MP_APBH_DMA] =3D { 0x33000000, 32 * KiB, "apbh_dma" }, + + /* AIPS-5 Begin */ + [FSL_IMX8MP_MU_3_B] =3D { 0x30e90000, 64 * KiB, "mu_3_b" }, + [FSL_IMX8MP_MU_3_A] =3D { 0x30e80000, 64 * KiB, "mu_3_a" }, + [FSL_IMX8MP_MU_2_B] =3D { 0x30e70000, 64 * KiB, "mu_2_b" }, + [FSL_IMX8MP_MU_2_A] =3D { 0x30e60000, 64 * KiB, "mu_2_a" }, + [FSL_IMX8MP_EDMA_CHANNELS] =3D { 0x30e40000, 128 * KiB, "edma_channels= " }, + [FSL_IMX8MP_EDMA_MANAGEMENT_PAGE] =3D { 0x30e30000, 64 * KiB, "edma_ma= nagement_page" }, + [FSL_IMX8MP_AUDIO_BLK_CTRL] =3D { 0x30e20000, 64 * KiB, "audio_blk_ctr= l" }, + [FSL_IMX8MP_SDMA2] =3D { 0x30e10000, 64 * KiB, "sdma2" }, + [FSL_IMX8MP_SDMA3] =3D { 0x30e00000, 64 * KiB, "sdma3" }, + [FSL_IMX8MP_AIPS5_CONFIGURATION] =3D { 0x30df0000, 64 * KiB, "aips5_co= nfiguration" }, + [FSL_IMX8MP_SPBA2] =3D { 0x30cf0000, 64 * KiB, "spba2" }, + [FSL_IMX8MP_AUDIO_XCVR_RX] =3D { 0x30cc0000, 64 * KiB, "audio_xcvr_rx"= }, + [FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR] =3D { 0x30cb0000, 64 * KiB, "hdmi_tx_= audlnk_mstr" }, + [FSL_IMX8MP_PDM] =3D { 0x30ca0000, 64 * KiB, "pdm" }, + [FSL_IMX8MP_ASRC] =3D { 0x30c90000, 64 * KiB, "asrc" }, + [FSL_IMX8MP_SAI7] =3D { 0x30c80000, 64 * KiB, "sai7" }, + [FSL_IMX8MP_SAI6] =3D { 0x30c60000, 64 * KiB, "sai6" }, + [FSL_IMX8MP_SAI5] =3D { 0x30c50000, 64 * KiB, "sai5" }, + [FSL_IMX8MP_SAI3] =3D { 0x30c30000, 64 * KiB, "sai3" }, + [FSL_IMX8MP_SAI2] =3D { 0x30c20000, 64 * KiB, "sai2" }, + [FSL_IMX8MP_SAI1] =3D { 0x30c10000, 64 * KiB, "sai1" }, + /* AIPS-5 End */ + + /* AIPS-4 Begin */ + [FSL_IMX8MP_HDMI_TX] =3D { 0x32fc0000, 128 * KiB, "hdmi_tx" }, + [FSL_IMX8MP_TZASC] =3D { 0x32f80000, 64 * KiB, "tzasc" }, + [FSL_IMX8MP_HSIO_BLK_CTL] =3D { 0x32f10000, 64 * KiB, "hsio_blk_ctl" }, + [FSL_IMX8MP_PCIE_PHY1] =3D { 0x32f00000, 64 * KiB, "pcie_phy1" }, + [FSL_IMX8MP_MEDIA_BLK_CTL] =3D { 0x32ec0000, 64 * KiB, "media_blk_ctl"= }, + [FSL_IMX8MP_LCDIF2] =3D { 0x32e90000, 64 * KiB, "lcdif2" }, + [FSL_IMX8MP_LCDIF1] =3D { 0x32e80000, 64 * KiB, "lcdif1" }, + [FSL_IMX8MP_MIPI_DSI1] =3D { 0x32e60000, 64 * KiB, "mipi_dsi1" }, + [FSL_IMX8MP_MIPI_CSI2] =3D { 0x32e50000, 64 * KiB, "mipi_csi2" }, + [FSL_IMX8MP_MIPI_CSI1] =3D { 0x32e40000, 64 * KiB, "mipi_csi1" }, + [FSL_IMX8MP_IPS_DEWARP] =3D { 0x32e30000, 64 * KiB, "ips_dewarp" }, + [FSL_IMX8MP_ISP2] =3D { 0x32e20000, 64 * KiB, "isp2" }, + [FSL_IMX8MP_ISP1] =3D { 0x32e10000, 64 * KiB, "isp1" }, + [FSL_IMX8MP_ISI] =3D { 0x32e00000, 64 * KiB, "isi" }, + [FSL_IMX8MP_AIPS4_CONFIGURATION] =3D { 0x32df0000, 64 * KiB, "aips4_co= nfiguration" }, + /* AIPS-4 End */ + + [FSL_IMX8MP_INTERCONNECT] =3D { 0x32700000, 1 * MiB, "interconnect" }, + + /* AIPS-3 Begin */ + [FSL_IMX8MP_ENET2_TSN] =3D { 0x30bf0000, 64 * KiB, "enet2_tsn" }, + [FSL_IMX8MP_ENET1] =3D { 0x30be0000, 64 * KiB, "enet1" }, + [FSL_IMX8MP_SDMA1] =3D { 0x30bd0000, 64 * KiB, "sdma1" }, + [FSL_IMX8MP_QSPI] =3D { 0x30bb0000, 64 * KiB, "qspi" }, + [FSL_IMX8MP_USDHC3] =3D { 0x30b60000, 64 * KiB, "usdhc3" }, + [FSL_IMX8MP_USDHC2] =3D { 0x30b50000, 64 * KiB, "usdhc2" }, + [FSL_IMX8MP_USDHC1] =3D { 0x30b40000, 64 * KiB, "usdhc1" }, + [FSL_IMX8MP_I2C6] =3D { 0x30ae0000, 64 * KiB, "i2c6" }, + [FSL_IMX8MP_I2C5] =3D { 0x30ad0000, 64 * KiB, "i2c5" }, + [FSL_IMX8MP_SEMAPHORE_HS] =3D { 0x30ac0000, 64 * KiB, "semaphore_hs" }, + [FSL_IMX8MP_MU_1_B] =3D { 0x30ab0000, 64 * KiB, "mu_1_b" }, + [FSL_IMX8MP_MU_1_A] =3D { 0x30aa0000, 64 * KiB, "mu_1_a" }, + [FSL_IMX8MP_AUD_IRQ_STEER] =3D { 0x30a80000, 64 * KiB, "aud_irq_steer"= }, + [FSL_IMX8MP_UART4] =3D { 0x30a60000, 64 * KiB, "uart4" }, + [FSL_IMX8MP_I2C4] =3D { 0x30a50000, 64 * KiB, "i2c4" }, + [FSL_IMX8MP_I2C3] =3D { 0x30a40000, 64 * KiB, "i2c3" }, + [FSL_IMX8MP_I2C2] =3D { 0x30a30000, 64 * KiB, "i2c2" }, + [FSL_IMX8MP_I2C1] =3D { 0x30a20000, 64 * KiB, "i2c1" }, + [FSL_IMX8MP_AIPS3_CONFIGURATION] =3D { 0x309f0000, 64 * KiB, "aips3_co= nfiguration" }, + [FSL_IMX8MP_CAAM] =3D { 0x30900000, 256 * KiB, "caam" }, + [FSL_IMX8MP_SPBA1] =3D { 0x308f0000, 64 * KiB, "spba1" }, + [FSL_IMX8MP_FLEXCAN2] =3D { 0x308d0000, 64 * KiB, "flexcan2" }, + [FSL_IMX8MP_FLEXCAN1] =3D { 0x308c0000, 64 * KiB, "flexcan1" }, + [FSL_IMX8MP_UART2] =3D { 0x30890000, 64 * KiB, "uart2" }, + [FSL_IMX8MP_UART3] =3D { 0x30880000, 64 * KiB, "uart3" }, + [FSL_IMX8MP_UART1] =3D { 0x30860000, 64 * KiB, "uart1" }, + [FSL_IMX8MP_ECSPI3] =3D { 0x30840000, 64 * KiB, "ecspi3" }, + [FSL_IMX8MP_ECSPI2] =3D { 0x30830000, 64 * KiB, "ecspi2" }, + [FSL_IMX8MP_ECSPI1] =3D { 0x30820000, 64 * KiB, "ecspi1" }, + /* AIPS-3 End */ + + /* AIPS-2 Begin */ + [FSL_IMX8MP_QOSC] =3D { 0x307f0000, 64 * KiB, "qosc" }, + [FSL_IMX8MP_PERFMON2] =3D { 0x307d0000, 64 * KiB, "perfmon2" }, + [FSL_IMX8MP_PERFMON1] =3D { 0x307c0000, 64 * KiB, "perfmon1" }, + [FSL_IMX8MP_GPT4] =3D { 0x30700000, 64 * KiB, "gpt4" }, + [FSL_IMX8MP_GPT5] =3D { 0x306f0000, 64 * KiB, "gpt5" }, + [FSL_IMX8MP_GPT6] =3D { 0x306e0000, 64 * KiB, "gpt6" }, + [FSL_IMX8MP_SYSCNT_CTRL] =3D { 0x306c0000, 64 * KiB, "syscnt_ctrl" }, + [FSL_IMX8MP_SYSCNT_CMP] =3D { 0x306b0000, 64 * KiB, "syscnt_cmp" }, + [FSL_IMX8MP_SYSCNT_RD] =3D { 0x306a0000, 64 * KiB, "syscnt_rd" }, + [FSL_IMX8MP_PWM4] =3D { 0x30690000, 64 * KiB, "pwm4" }, + [FSL_IMX8MP_PWM3] =3D { 0x30680000, 64 * KiB, "pwm3" }, + [FSL_IMX8MP_PWM2] =3D { 0x30670000, 64 * KiB, "pwm2" }, + [FSL_IMX8MP_PWM1] =3D { 0x30660000, 64 * KiB, "pwm1" }, + [FSL_IMX8MP_AIPS2_CONFIGURATION] =3D { 0x305f0000, 64 * KiB, "aips2_co= nfiguration" }, + /* AIPS-2 End */ + + /* AIPS-1 Begin */ + [FSL_IMX8MP_CSU] =3D { 0x303e0000, 64 * KiB, "csu" }, + [FSL_IMX8MP_RDC] =3D { 0x303d0000, 64 * KiB, "rdc" }, + [FSL_IMX8MP_SEMAPHORE2] =3D { 0x303c0000, 64 * KiB, "semaphore2" }, + [FSL_IMX8MP_SEMAPHORE1] =3D { 0x303b0000, 64 * KiB, "semaphore1" }, + [FSL_IMX8MP_GPC] =3D { 0x303a0000, 64 * KiB, "gpc" }, + [FSL_IMX8MP_SRC] =3D { 0x30390000, 64 * KiB, "src" }, + [FSL_IMX8MP_CCM] =3D { 0x30380000, 64 * KiB, "ccm" }, + [FSL_IMX8MP_SNVS_HP] =3D { 0x30370000, 64 * KiB, "snvs_hp" }, + [FSL_IMX8MP_ANA_PLL] =3D { 0x30360000, 64 * KiB, "ana_pll" }, + [FSL_IMX8MP_OCOTP_CTRL] =3D { 0x30350000, 64 * KiB, "ocotp_ctrl" }, + [FSL_IMX8MP_IOMUXC_GPR] =3D { 0x30340000, 64 * KiB, "iomuxc_gpr" }, + [FSL_IMX8MP_IOMUXC] =3D { 0x30330000, 64 * KiB, "iomuxc" }, + [FSL_IMX8MP_GPT3] =3D { 0x302f0000, 64 * KiB, "gpt3" }, + [FSL_IMX8MP_GPT2] =3D { 0x302e0000, 64 * KiB, "gpt2" }, + [FSL_IMX8MP_GPT1] =3D { 0x302d0000, 64 * KiB, "gpt1" }, + [FSL_IMX8MP_WDOG3] =3D { 0x302a0000, 64 * KiB, "wdog3" }, + [FSL_IMX8MP_WDOG2] =3D { 0x30290000, 64 * KiB, "wdog2" }, + [FSL_IMX8MP_WDOG1] =3D { 0x30280000, 64 * KiB, "wdog1" }, + [FSL_IMX8MP_ANA_OSC] =3D { 0x30270000, 64 * KiB, "ana_osc" }, + [FSL_IMX8MP_ANA_TSENSOR] =3D { 0x30260000, 64 * KiB, "ana_tsensor" }, + [FSL_IMX8MP_GPIO5] =3D { 0x30240000, 64 * KiB, "gpio5" }, + [FSL_IMX8MP_GPIO4] =3D { 0x30230000, 64 * KiB, "gpio4" }, + [FSL_IMX8MP_GPIO3] =3D { 0x30220000, 64 * KiB, "gpio3" }, + [FSL_IMX8MP_GPIO2] =3D { 0x30210000, 64 * KiB, "gpio2" }, + [FSL_IMX8MP_GPIO1] =3D { 0x30200000, 64 * KiB, "gpio1" }, + [FSL_IMX8MP_AIPS1_CONFIGURATION] =3D { 0x301f0000, 64 * KiB, "aips1_co= nfiguration" }, + /* AIPS-1 End */ + + [FSL_IMX8MP_A53_DAP] =3D { 0x28000000, 16 * MiB, "a53_dap" }, + [FSL_IMX8MP_PCIE1_MEM] =3D { 0x18000000, 128 * MiB, "pcie1_mem" }, + [FSL_IMX8MP_QSPI_MEM] =3D { 0x08000000, 256 * MiB, "qspi_mem" }, + [FSL_IMX8MP_OCRAM] =3D { 0x00900000, 576 * KiB, "ocram" }, + [FSL_IMX8MP_TCM_DTCM] =3D { 0x00800000, 128 * KiB, "tcm_dtcm" }, + [FSL_IMX8MP_TCM_ITCM] =3D { 0x007e0000, 128 * KiB, "tcm_itcm" }, + [FSL_IMX8MP_OCRAM_S] =3D { 0x00180000, 36 * KiB, "ocram_s" }, + [FSL_IMX8MP_CAAM_MEM] =3D { 0x00100000, 32 * KiB, "caam_mem" }, + [FSL_IMX8MP_BOOT_ROM_PROTECTED] =3D { 0x0003f000, 4 * KiB, "boot_rom_p= rotected" }, + [FSL_IMX8MP_BOOT_ROM] =3D { 0x00000000, 252 * KiB, "boot_rom" }, +}; + +#define NAME_SIZE 20 + +static void fsl_imx8mp_init(Object *obj) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + FslImx8mpState *s =3D FSL_IMX8MP(obj); + char name[NAME_SIZE]; + int i; + + for (i =3D 0; i < MIN(ms->smp.cpus, FSL_IMX8MP_NUM_CPUS); i++) { + snprintf(name, NAME_SIZE, "cpu%d", i); + object_initialize_child(obj, name, &s->cpu[i], + ARM_CPU_TYPE_NAME("cortex-a53")); + } + + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3); + + for (i =3D 0; i < FSL_IMX8MP_NUM_UARTS; i++) { + snprintf(name, NAME_SIZE, "uart%d", i + 1); + object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); + } +} + +static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + FslImx8mpState *s =3D FSL_IMX8MP(dev); + DeviceState *gicdev =3D DEVICE(&s->gic); + int i; + + if (ms->smp.cpus > FSL_IMX8MP_NUM_CPUS) { + error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", + TYPE_FSL_IMX8MP, FSL_IMX8MP_NUM_CPUS, ms->smp.cpus); + return; + } + + /* CPUs */ + for (i =3D 0; i < ms->smp.cpus; i++) { + /* On uniprocessor, the CBAR is set to 0 */ + if (ms->smp.cpus > 1) { + object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", + fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST]= .addr, + &error_abort); + } + + /* + * Magic value from Linux output: "arch_timer: cp15 timer(s) runni= ng at + * 8.00MHz (phys)". + */ + object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, + &error_abort); + + if (i) { + /* + * Secondary CPUs start in powered-down state (and can be + * powered up via the SRC system reset controller) + */ + object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-of= f", + true, &error_abort); + } + + if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + return; + } + } + + /* GIC */ + { + SysBusDevice *gicsbd =3D SYS_BUS_DEVICE(&s->gic); + QList *redist_region_count; + + qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus); + qdev_prop_set_uint32(gicdev, "num-irq", + FSL_IMX8MP_NUM_IRQS + GIC_INTERNAL); + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, ms->smp.cpus); + qdev_prop_set_array(gicdev, "redist-region-count", redist_region_c= ount); + object_property_set_link(OBJECT(&s->gic), "sysmem", + OBJECT(get_system_memory()), &error_fatal= ); + if (!sysbus_realize(gicsbd, errp)) { + return; + } + sysbus_mmio_map(gicsbd, 0, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].= addr); + sysbus_mmio_map(gicsbd, 1, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_REDIST= ].addr); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs,= and + * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs. + */ + for (i =3D 0; i < ms->smp.cpus; i++) { + DeviceState *cpudev =3D DEVICE(&s->cpu[i]); + int intidbase =3D FSL_IMX8MP_NUM_IRQS + i * GIC_INTERNAL; + qemu_irq irq; + + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs. + */ + static const int timer_irqs[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + + for (int j =3D 0; j < ARRAY_SIZE(timer_irqs); j++) { + irq =3D qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]= ); + qdev_connect_gpio_out(cpudev, j, irq); + } + + irq =3D qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IR= Q); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + + irq =3D qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq); + + sysbus_connect_irq(gicsbd, i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(gicsbd, i + ms->smp.cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + } + } + + /* UARTs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_UARTS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } serial_table[FSL_IMX8MP_NUM_UARTS] =3D { + { fsl_imx8mp_memmap[FSL_IMX8MP_UART1].addr, FSL_IMX8MP_UART1_I= RQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_UART2].addr, FSL_IMX8MP_UART2_I= RQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_UART3].addr, FSL_IMX8MP_UART3_I= RQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_UART4].addr, FSL_IMX8MP_UART4_I= RQ }, + }; + + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].ad= dr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + qdev_get_gpio_in(gicdev, serial_table[i].irq)); + } + + /* Unimplemented devices */ + for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { + switch (i) { + case FSL_IMX8MP_GIC_DIST: + case FSL_IMX8MP_GIC_REDIST: + case FSL_IMX8MP_RAM: + case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4: + /* device implemented and treated above */ + break; + + default: + create_unimplemented_device(fsl_imx8mp_memmap[i].name, + fsl_imx8mp_memmap[i].addr, + fsl_imx8mp_memmap[i].size); + break; + } + } +} + +static void fsl_imx8mp_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D fsl_imx8mp_realize; + + dc->desc =3D "i.MX 8M Plus SoC"; +} + +static const TypeInfo fsl_imx8mp_types[] =3D { + { + .name =3D TYPE_FSL_IMX8MP, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(FslImx8mpState), + .instance_init =3D fsl_imx8mp_init, + .class_init =3D fsl_imx8mp_class_init, + }, +}; + +DEFINE_TYPES(fsl_imx8mp_types) diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c new file mode 100644 index 0000000000..2756d4c21c --- /dev/null +++ b/hw/arm/imx8mp-evk.c @@ -0,0 +1,55 @@ +/* + * NXP i.MX 8M Plus Evaluation Kit System Emulation + * + * Copyright (c) 2024, Bernhard Beschow + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/address-spaces.h" +#include "hw/arm/boot.h" +#include "hw/arm/fsl-imx8mp.h" +#include "hw/boards.h" +#include "system/qtest.h" +#include "qemu/error-report.h" +#include "qapi/error.h" + +static void imx8mp_evk_init(MachineState *machine) +{ + static struct arm_boot_info boot_info; + FslImx8mpState *s; + + if (machine->ram_size > FSL_IMX8MP_RAM_SIZE_MAX) { + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08" = PRIx64 ")", + machine->ram_size, FSL_IMX8MP_RAM_SIZE_MAX); + exit(1); + } + + boot_info =3D (struct arm_boot_info) { + .loader_start =3D FSL_IMX8MP_RAM_START, + .board_id =3D -1, + .ram_size =3D machine->ram_size, + .psci_conduit =3D QEMU_PSCI_CONDUIT_SMC, + }; + + s =3D FSL_IMX8MP(object_new(TYPE_FSL_IMX8MP)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + qdev_realize(DEVICE(s), NULL, &error_fatal); + + memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START, + machine->ram); + + if (!qtest_enabled()) { + arm_load_kernel(&s->cpu[0], machine, &boot_info); + } +} + +static void imx8mp_evk_machine_init(MachineClass *mc) +{ + mc->desc =3D "NXP i.MX 8M Plus EVK Board"; + mc->init =3D imx8mp_evk_init; + mc->max_cpus =3D FSL_IMX8MP_NUM_CPUS; + mc->default_ram_id =3D "imx8mp-evk.ram"; +} +DEFINE_MACHINE("imx8mp-evk", imx8mp_evk_machine_init) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 256013ca80..e22916df57 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -577,6 +577,18 @@ config FSL_IMX7 select OR_IRQ select UNIMP =20 +config FSL_IMX8MP + bool + select ARM_GIC + select IMX + select UNIMP + +config FSL_IMX8MP_EVK + bool + default y + depends on TCG && AARCH64 + select FSL_IMX8MP + config ARM_SMMUV3 bool =20 diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 490234b3b8..79750ae7b1 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -53,6 +53,8 @@ arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.= c')) arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-= sabre.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcim= x6ul-evk.c')) arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Also provides= the clocks for devices added later, e.g. enet1. Signed-off-by: Bernhard Beschow --- MAINTAINERS | 2 + docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 4 + include/hw/misc/imx8mp_analog.h | 81 +++++++++++++++ include/hw/misc/imx8mp_ccm.h | 30 ++++++ hw/arm/fsl-imx8mp.c | 20 ++++ hw/misc/imx8mp_analog.c | 160 +++++++++++++++++++++++++++++ hw/misc/imx8mp_ccm.c | 175 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 + hw/misc/Kconfig | 6 ++ hw/misc/meson.build | 2 + 11 files changed, 483 insertions(+) create mode 100644 include/hw/misc/imx8mp_analog.h create mode 100644 include/hw/misc/imx8mp_ccm.h create mode 100644 hw/misc/imx8mp_analog.c create mode 100644 hw/misc/imx8mp_ccm.c diff --git a/MAINTAINERS b/MAINTAINERS index 8db59114bc..5b5b0d0bed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -826,7 +826,9 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/imx8mp-evk.c F: hw/arm/fsl-imx8mp.c +F: hw/misc/imx8mp_*.c F: include/hw/arm/fsl-imx8mp.h +F: include/hw/misc/imx8mp_*.h F: docs/system/arm/imx8mp-evk.rst =20 MPS2 / MPS3 diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index a9c1fab390..e5039fc8c4 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -13,6 +13,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * Up to 4 Cortex-A53 Cores * Generic Interrupt Controller (GICv3) * 4 UARTs + * Clock Tree =20 Boot options ------------ diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 57e23d1b69..ce5188e7f2 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -12,6 +12,8 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/misc/imx8mp_analog.h" +#include "hw/misc/imx8mp_ccm.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -32,6 +34,8 @@ struct FslImx8mpState { =20 ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; GICv3State gic; + IMX8MPCCMState ccm; + IMX8MPAnalogState analog; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; }; =20 diff --git a/include/hw/misc/imx8mp_analog.h b/include/hw/misc/imx8mp_analo= g.h new file mode 100644 index 0000000000..955f03215a --- /dev/null +++ b/include/hw/misc/imx8mp_analog.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2025 Bernhard Beschow + * + * i.MX8MP ANALOG IP block emulation code + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef IMX8MP_ANALOG_H +#define IMX8MP_ANALOG_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +enum IMX8MPAnalogRegisters { + ANALOG_AUDIO_PLL1_GEN_CTRL =3D 0x000 / 4, + ANALOG_AUDIO_PLL1_FDIV_CTL0 =3D 0x004 / 4, + ANALOG_AUDIO_PLL1_FDIV_CTL1 =3D 0x008 / 4, + ANALOG_AUDIO_PLL1_SSCG_CTRL =3D 0x00c / 4, + ANALOG_AUDIO_PLL1_MNIT_CTRL =3D 0x010 / 4, + ANALOG_AUDIO_PLL2_GEN_CTRL =3D 0x014 / 4, + ANALOG_AUDIO_PLL2_FDIV_CTL0 =3D 0x018 / 4, + ANALOG_AUDIO_PLL2_FDIV_CTL1 =3D 0x01c / 4, + ANALOG_AUDIO_PLL2_SSCG_CTRL =3D 0x020 / 4, + ANALOG_AUDIO_PLL2_MNIT_CTRL =3D 0x024 / 4, + ANALOG_VIDEO_PLL1_GEN_CTRL =3D 0x028 / 4, + ANALOG_VIDEO_PLL1_FDIV_CTL0 =3D 0x02c / 4, + ANALOG_VIDEO_PLL1_FDIV_CTL1 =3D 0x030 / 4, + ANALOG_VIDEO_PLL1_SSCG_CTRL =3D 0x034 / 4, + ANALOG_VIDEO_PLL1_MNIT_CTRL =3D 0x038 / 4, + ANALOG_DRAM_PLL_GEN_CTRL =3D 0x050 / 4, + ANALOG_DRAM_PLL_FDIV_CTL0 =3D 0x054 / 4, + ANALOG_DRAM_PLL_FDIV_CTL1 =3D 0x058 / 4, + ANALOG_DRAM_PLL_SSCG_CTRL =3D 0x05c / 4, + ANALOG_DRAM_PLL_MNIT_CTRL =3D 0x060 / 4, + ANALOG_GPU_PLL_GEN_CTRL =3D 0x064 / 4, + ANALOG_GPU_PLL_FDIV_CTL0 =3D 0x068 / 4, + ANALOG_GPU_PLL_LOCKD_CTRL =3D 0x06c / 4, + ANALOG_GPU_PLL_MNIT_CTRL =3D 0x070 / 4, + ANALOG_VPU_PLL_GEN_CTRL =3D 0x074 / 4, + ANALOG_VPU_PLL_FDIV_CTL0 =3D 0x078 / 4, + ANALOG_VPU_PLL_LOCKD_CTRL =3D 0x07c / 4, + ANALOG_VPU_PLL_MNIT_CTRL =3D 0x080 / 4, + ANALOG_ARM_PLL_GEN_CTRL =3D 0x084 / 4, + ANALOG_ARM_PLL_FDIV_CTL0 =3D 0x088 / 4, + ANALOG_ARM_PLL_LOCKD_CTRL =3D 0x08c / 4, + ANALOG_ARM_PLL_MNIT_CTRL =3D 0x090 / 4, + ANALOG_SYS_PLL1_GEN_CTRL =3D 0x094 / 4, + ANALOG_SYS_PLL1_FDIV_CTL0 =3D 0x098 / 4, + ANALOG_SYS_PLL1_LOCKD_CTRL =3D 0x09c / 4, + ANALOG_SYS_PLL1_MNIT_CTRL =3D 0x100 / 4, + ANALOG_SYS_PLL2_GEN_CTRL =3D 0x104 / 4, + ANALOG_SYS_PLL2_FDIV_CTL0 =3D 0x108 / 4, + ANALOG_SYS_PLL2_LOCKD_CTRL =3D 0x10c / 4, + ANALOG_SYS_PLL2_MNIT_CTRL =3D 0x110 / 4, + ANALOG_SYS_PLL3_GEN_CTRL =3D 0x114 / 4, + ANALOG_SYS_PLL3_FDIV_CTL0 =3D 0x118 / 4, + ANALOG_SYS_PLL3_LOCKD_CTRL =3D 0x11c / 4, + ANALOG_SYS_PLL3_MNIT_CTRL =3D 0x120 / 4, + ANALOG_OSC_MISC_CFG =3D 0x124 / 4, + ANALOG_ANAMIX_PLL_MNIT_CTL =3D 0x128 / 4, + + ANALOG_DIGPROG =3D 0x800 / 4, + ANALOG_MAX, +}; + +#define TYPE_IMX8MP_ANALOG "imx8mp.analog" +OBJECT_DECLARE_SIMPLE_TYPE(IMX8MPAnalogState, IMX8MP_ANALOG) + +struct IMX8MPAnalogState { + SysBusDevice parent_obj; + + struct { + MemoryRegion container; + MemoryRegion analog; + } mmio; + + uint32_t analog[ANALOG_MAX]; +}; + +#endif /* IMX8MP_ANALOG_H */ diff --git a/include/hw/misc/imx8mp_ccm.h b/include/hw/misc/imx8mp_ccm.h new file mode 100644 index 0000000000..685c8582ff --- /dev/null +++ b/include/hw/misc/imx8mp_ccm.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Bernhard Beschow + * + * i.MX 8M Plus CCM IP block emulation code + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef IMX8MP_CCM_H +#define IMX8MP_CCM_H + +#include "hw/misc/imx_ccm.h" +#include "qom/object.h" + +enum IMX8MPCCMRegisters { + CCM_MAX =3D 0xc6fc / sizeof(uint32_t) + 1, +}; + +#define TYPE_IMX8MP_CCM "imx8mp.ccm" +OBJECT_DECLARE_SIMPLE_TYPE(IMX8MPCCMState, IMX8MP_CCM) + +struct IMX8MPCCMState { + IMXCCMState parent_obj; + + MemoryRegion iomem; + + uint32_t ccm[CCM_MAX]; +}; + +#endif /* IMX8MP_CCM_H */ diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 0836d82ca0..a1a8843b3b 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -200,6 +200,10 @@ static void fsl_imx8mp_init(Object *obj) =20 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GICV3); =20 + object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM); + + object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG); + for (i =3D 0; i < FSL_IMX8MP_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); @@ -308,6 +312,20 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) } } =20 + /* CCM */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_CCM].addr); + + /* Analog */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_ANA_PLL].addr); + /* UARTs */ for (i =3D 0; i < FSL_IMX8MP_NUM_UARTS; i++) { static const struct { @@ -333,6 +351,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { switch (i) { + case FSL_IMX8MP_ANA_PLL: + case FSL_IMX8MP_CCM: case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_RAM: diff --git a/hw/misc/imx8mp_analog.c b/hw/misc/imx8mp_analog.c new file mode 100644 index 0000000000..71333b3e9e --- /dev/null +++ b/hw/misc/imx8mp_analog.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2025 Bernhard Beschow + * + * i.MX 8M Plus ANALOG IP block emulation code + * + * Based on hw/misc/imx7_ccm.c + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" + +#include "hw/misc/imx8mp_analog.h" +#include "migration/vmstate.h" + +#define ANALOG_PLL_LOCK BIT(31) + +static void imx8mp_analog_reset(DeviceState *dev) +{ + IMX8MPAnalogState *s =3D IMX8MP_ANALOG(dev); + + memset(s->analog, 0, sizeof(s->analog)); + + s->analog[ANALOG_AUDIO_PLL1_GEN_CTRL] =3D 0x00002010; + s->analog[ANALOG_AUDIO_PLL1_FDIV_CTL0] =3D 0x00145032; + s->analog[ANALOG_AUDIO_PLL1_FDIV_CTL1] =3D 0x00000000; + s->analog[ANALOG_AUDIO_PLL1_SSCG_CTRL] =3D 0x00000000; + s->analog[ANALOG_AUDIO_PLL1_MNIT_CTRL] =3D 0x00100103; + s->analog[ANALOG_AUDIO_PLL2_GEN_CTRL] =3D 0x00002010; + s->analog[ANALOG_AUDIO_PLL2_FDIV_CTL0] =3D 0x00145032; + s->analog[ANALOG_AUDIO_PLL2_FDIV_CTL1] =3D 0x00000000; + s->analog[ANALOG_AUDIO_PLL2_SSCG_CTRL] =3D 0x00000000; + s->analog[ANALOG_AUDIO_PLL2_MNIT_CTRL] =3D 0x00100103; + s->analog[ANALOG_VIDEO_PLL1_GEN_CTRL] =3D 0x00002010; + s->analog[ANALOG_VIDEO_PLL1_FDIV_CTL0] =3D 0x00145032; + s->analog[ANALOG_VIDEO_PLL1_FDIV_CTL1] =3D 0x00000000; + s->analog[ANALOG_VIDEO_PLL1_SSCG_CTRL] =3D 0x00000000; + s->analog[ANALOG_VIDEO_PLL1_MNIT_CTRL] =3D 0x00100103; + s->analog[ANALOG_DRAM_PLL_GEN_CTRL] =3D 0x00002010; + s->analog[ANALOG_DRAM_PLL_FDIV_CTL0] =3D 0x0012c032; + s->analog[ANALOG_DRAM_PLL_FDIV_CTL1] =3D 0x00000000; + s->analog[ANALOG_DRAM_PLL_SSCG_CTRL] =3D 0x00000000; + s->analog[ANALOG_DRAM_PLL_MNIT_CTRL] =3D 0x00100103; + s->analog[ANALOG_GPU_PLL_GEN_CTRL] =3D 0x00000810; + s->analog[ANALOG_GPU_PLL_FDIV_CTL0] =3D 0x000c8031; + s->analog[ANALOG_GPU_PLL_LOCKD_CTRL] =3D 0x0010003f; + s->analog[ANALOG_GPU_PLL_MNIT_CTRL] =3D 0x00280081; + s->analog[ANALOG_VPU_PLL_GEN_CTRL] =3D 0x00000810; + s->analog[ANALOG_VPU_PLL_FDIV_CTL0] =3D 0x0012c032; + s->analog[ANALOG_VPU_PLL_LOCKD_CTRL] =3D 0x0010003f; + s->analog[ANALOG_VPU_PLL_MNIT_CTRL] =3D 0x00280081; + s->analog[ANALOG_ARM_PLL_GEN_CTRL] =3D 0x00000810; + s->analog[ANALOG_ARM_PLL_FDIV_CTL0] =3D 0x000fa031; + s->analog[ANALOG_ARM_PLL_LOCKD_CTRL] =3D 0x0010003f; + s->analog[ANALOG_ARM_PLL_MNIT_CTRL] =3D 0x00280081; + s->analog[ANALOG_SYS_PLL1_GEN_CTRL] =3D 0x0aaaa810; + s->analog[ANALOG_SYS_PLL1_FDIV_CTL0] =3D 0x00190032; + s->analog[ANALOG_SYS_PLL1_LOCKD_CTRL] =3D 0x0010003f; + s->analog[ANALOG_SYS_PLL1_MNIT_CTRL] =3D 0x00280081; + s->analog[ANALOG_SYS_PLL2_GEN_CTRL] =3D 0x0aaaa810; + s->analog[ANALOG_SYS_PLL2_FDIV_CTL0] =3D 0x000fa031; + s->analog[ANALOG_SYS_PLL2_LOCKD_CTRL] =3D 0x0010003f; + s->analog[ANALOG_SYS_PLL2_MNIT_CTRL] =3D 0x00280081; + s->analog[ANALOG_SYS_PLL3_GEN_CTRL] =3D 0x00000810; + s->analog[ANALOG_SYS_PLL3_FDIV_CTL0] =3D 0x000fa031; + s->analog[ANALOG_SYS_PLL3_LOCKD_CTRL] =3D 0x0010003f; + s->analog[ANALOG_SYS_PLL3_MNIT_CTRL] =3D 0x00280081; + s->analog[ANALOG_OSC_MISC_CFG] =3D 0x00000000; + s->analog[ANALOG_ANAMIX_PLL_MNIT_CTL] =3D 0x00000000; + s->analog[ANALOG_DIGPROG] =3D 0x00824010; + + /* all PLLs need to be locked */ + s->analog[ANALOG_AUDIO_PLL1_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_AUDIO_PLL2_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_VIDEO_PLL1_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_DRAM_PLL_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_GPU_PLL_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_VPU_PLL_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_ARM_PLL_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_SYS_PLL1_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_SYS_PLL2_GEN_CTRL] |=3D ANALOG_PLL_LOCK; + s->analog[ANALOG_SYS_PLL3_GEN_CTRL] |=3D ANALOG_PLL_LOCK; +} + +static uint64_t imx8mp_analog_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + IMX8MPAnalogState *s =3D opaque; + + return s->analog[offset >> 2]; +} + +static void imx8mp_analog_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + IMX8MPAnalogState *s =3D opaque; + + if (offset >> 2 =3D=3D ANALOG_DIGPROG) { + qemu_log_mask(LOG_GUEST_ERROR, + "Guest write to read-only ANALOG_DIGPROG register\n"= ); + } else { + s->analog[offset >> 2] =3D value; + } +} + +static const struct MemoryRegionOps imx8mp_analog_ops =3D { + .read =3D imx8mp_analog_read, + .write =3D imx8mp_analog_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx8mp_analog_init(Object *obj) +{ + IMX8MPAnalogState *s =3D IMX8MP_ANALOG(obj); + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + + memory_region_init(&s->mmio.container, obj, TYPE_IMX8MP_ANALOG, 0x1000= 0); + + memory_region_init_io(&s->mmio.analog, obj, &imx8mp_analog_ops, s, + TYPE_IMX8MP_ANALOG, sizeof(s->analog)); + memory_region_add_subregion(&s->mmio.container, 0, &s->mmio.analog); + + sysbus_init_mmio(sd, &s->mmio.container); +} + +static const VMStateDescription vmstate_imx8mp_analog =3D { + .name =3D TYPE_IMX8MP_ANALOG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(analog, IMX8MPAnalogState, ANALOG_MAX), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx8mp_analog_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, imx8mp_analog_reset); + dc->vmsd =3D &vmstate_imx8mp_analog; + dc->desc =3D "i.MX 8M Plus Analog Module"; +} + +static const TypeInfo imx8mp_ccm_types[] =3D { + { + .name =3D TYPE_IMX8MP_ANALOG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX8MPAnalogState), + .instance_init =3D imx8mp_analog_init, + .class_init =3D imx8mp_analog_class_init, + } +}; + +DEFINE_TYPES(imx8mp_ccm_types); diff --git a/hw/misc/imx8mp_ccm.c b/hw/misc/imx8mp_ccm.c new file mode 100644 index 0000000000..7c869ff86b --- /dev/null +++ b/hw/misc/imx8mp_ccm.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2025 Bernhard Beschow + * + * i.MX 8M Plus CCM IP block emulation code + * + * Based on hw/misc/imx7_ccm.c + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" + +#include "hw/misc/imx8mp_ccm.h" +#include "migration/vmstate.h" + +#include "trace.h" + +#define CKIH_FREQ 16000000 /* 16MHz crystal input */ + +static void imx8mp_ccm_reset(DeviceState *dev) +{ + IMX8MPCCMState *s =3D IMX8MP_CCM(dev); + + memset(s->ccm, 0, sizeof(s->ccm)); +} + +#define CCM_INDEX(offset) (((offset) & ~(hwaddr)0xF) / sizeof(uint32_t)) +#define CCM_BITOP(offset) ((offset) & (hwaddr)0xF) + +enum { + CCM_BITOP_NONE =3D 0x00, + CCM_BITOP_SET =3D 0x04, + CCM_BITOP_CLR =3D 0x08, + CCM_BITOP_TOG =3D 0x0C, +}; + +static uint64_t imx8mp_set_clr_tog_read(void *opaque, hwaddr offset, + unsigned size) +{ + const uint32_t *mmio =3D opaque; + + return mmio[CCM_INDEX(offset)]; +} + +static void imx8mp_set_clr_tog_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + const uint8_t bitop =3D CCM_BITOP(offset); + const uint32_t index =3D CCM_INDEX(offset); + uint32_t *mmio =3D opaque; + + switch (bitop) { + case CCM_BITOP_NONE: + mmio[index] =3D value; + break; + case CCM_BITOP_SET: + mmio[index] |=3D value; + break; + case CCM_BITOP_CLR: + mmio[index] &=3D ~value; + break; + case CCM_BITOP_TOG: + mmio[index] ^=3D value; + break; + }; +} + +static const struct MemoryRegionOps imx8mp_set_clr_tog_ops =3D { + .read =3D imx8mp_set_clr_tog_read, + .write =3D imx8mp_set_clr_tog_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx8mp_ccm_init(Object *obj) +{ + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + IMX8MPCCMState *s =3D IMX8MP_CCM(obj); + + memory_region_init_io(&s->iomem, + obj, + &imx8mp_set_clr_tog_ops, + s->ccm, + TYPE_IMX8MP_CCM ".ccm", + sizeof(s->ccm)); + + sysbus_init_mmio(sd, &s->iomem); +} + +static const VMStateDescription vmstate_imx8mp_ccm =3D { + .name =3D TYPE_IMX8MP_CCM, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(ccm, IMX8MPCCMState, CCM_MAX), + VMSTATE_END_OF_LIST() + }, +}; + +static uint32_t imx8mp_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk cl= ock) +{ + /* + * This function is "consumed" by GPT emulation code. Some clocks + * have fixed frequencies and we can provide requested frequency + * easily. However for CCM provided clocks (like IPG) each GPT + * timer can have its own clock root. + * This means we need additional information when calling this + * function to know the requester's identity. + */ + uint32_t freq =3D 0; + + switch (clock) { + case CLK_NONE: + break; + case CLK_32k: + freq =3D CKIL_FREQ; + break; + case CLK_HIGH: + freq =3D CKIH_FREQ; + break; + case CLK_IPG: + case CLK_IPG_HIGH: + /* + * For now we don't have a way to figure out the device this + * function is called for. Until then the IPG derived clocks + * are left unimplemented. + */ + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n= ", + TYPE_IMX8MP_CCM, __func__, clock); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n", + TYPE_IMX8MP_CCM, __func__, clock); + break; + } + + trace_ccm_clock_freq(clock, freq); + + return freq; +} + +static void imx8mp_ccm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + IMXCCMClass *ccm =3D IMX_CCM_CLASS(klass); + + device_class_set_legacy_reset(dc, imx8mp_ccm_reset); + dc->vmsd =3D &vmstate_imx8mp_ccm; + dc->desc =3D "i.MX 8M Plus Clock Control Module"; + + ccm->get_clock_frequency =3D imx8mp_ccm_get_clock_frequency; +} + +static const TypeInfo imx8mp_ccm_types[] =3D { + { + .name =3D TYPE_IMX8MP_CCM, + .parent =3D TYPE_IMX_CCM, + .instance_size =3D sizeof(IMX8MPCCMState), + .instance_init =3D imx8mp_ccm_init, + .class_init =3D imx8mp_ccm_class_init, + }, +}; + +DEFINE_TYPES(imx8mp_ccm_types); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e22916df57..0079c51734 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -580,6 +580,8 @@ config FSL_IMX7 config FSL_IMX8MP bool select ARM_GIC + select FSL_IMX8MP_ANALOG + select FSL_IMX8MP_CCM select IMX select UNIMP =20 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 4271e2f4ac..82bd68b4bb 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -78,6 +78,12 @@ config IMX select SSI select USB_EHCI_SYSBUS =20 +config FSL_IMX8MP_ANALOG + bool + +config FSL_IMX8MP_CCM + bool + config STM32_RCC bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 55f493521b..f9285cf2f1 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -55,6 +55,8 @@ system_ss.add(when: 'CONFIG_AXP2XX_PMU', if_true: files('= axp2xx.c')) system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c')) system_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c')) system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_pmu.c', '= exynos4210_clk.c', 'exynos4210_rng.c')) +system_ss.add(when: 'CONFIG_FSL_IMX8MP_ANALOG', if_true: files('imx8mp_ana= log.c')) +system_ss.add(when: 'CONFIG_FSL_IMX8MP_CCM', if_true: files('imx8mp_ccm.c'= )) system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx25_ccm.c', 'imx31_ccm.c', --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738661053; cv=none; d=zohomail.com; s=zohoarc; b=oAVMi+x1tZDtcCvqHbF6WFTFBpx8G5A1yPaIaaUH/VjZIUTu0H+b9Nhfsbzsg4jzq5FpjvjyzJwhQdMz7VQj6ZtR2xKTrcju3tHz7f97vYEGYZDJ9i9MplNUHocrqHju29lHijM7ssGp2LRdCY40ogUqvQn6aPkKMkkfGMommdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738661053; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tANkBi6sQeQ6AT/ajHf/OcJmWhoX7n1olSXdynh3fXk=; b=DqBdWgk95etD/C393RwcxvSae4VNZgI6ikIBsZWYqTXTROKxJjplIux3wiep+eI385d7mW5hJjnXA1QykcMUA9pBjXXby7pUxJiIPCo7Hx8WVOkjfTPhNmkaWJCAsrPF+69bUP3Pm2P2tUz1tOfJTG/gBXEu6GnL9/jxe4o97to= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738661053574333.82497410614155; Tue, 4 Feb 2025 01:24:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF7d-0004nH-UT; Tue, 04 Feb 2025 04:21:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7c-0004ml-M8; Tue, 04 Feb 2025 04:21:32 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7a-00053l-Sg; Tue, 04 Feb 2025 04:21:32 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-43635796b48so32681335e9.0; Tue, 04 Feb 2025 01:21:30 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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This is particularly useful when handling persistent storage which will be done in = the next patch. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 2 ++ hw/arm/fsl-imx8mp.c | 10 ++++++++++ 3 files changed, 13 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index e5039fc8c4..8f1237c74e 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -13,6 +13,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * Up to 4 Cortex-A53 Cores * Generic Interrupt Controller (GICv3) * 4 UARTs + * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 Boot options diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index ce5188e7f2..26e24e99a1 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -12,6 +12,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" #include "qom/object.h" @@ -36,6 +37,7 @@ struct FslImx8mpState { GICv3State gic; IMX8MPCCMState ccm; IMX8MPAnalogState analog; + IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; }; =20 diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index a1a8843b3b..32ca76c671 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -204,6 +204,8 @@ static void fsl_imx8mp_init(Object *obj) =20 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG); =20 + object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); + for (i =3D 0; i < FSL_IMX8MP_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); @@ -348,6 +350,13 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } =20 + /* SNVS */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { switch (i) { @@ -356,6 +365,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_RAM: + case FSL_IMX8MP_SNVS_HP: case FSL_IMX8MP_UART1 ... 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Convert the board documentation accordingly instead of runnin= g a Linux kernel with ephemeral storage. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 16 +++++++++++----- include/hw/arm/fsl-imx8mp.h | 7 +++++++ hw/arm/fsl-imx8mp.c | 28 ++++++++++++++++++++++++++++ hw/arm/imx8mp-evk.c | 18 ++++++++++++++++++ hw/arm/Kconfig | 1 + 5 files changed, 65 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 8f1237c74e..475c42d76a 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -13,6 +13,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * Up to 4 Cortex-A53 Cores * Generic Interrupt Controller (GICv3) * 4 UARTs + * 3 USDHC Storage Controllers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 @@ -27,17 +28,22 @@ Direct Linux Kernel Boot =20 Probably the easiest way to get started with a whole Linux system on the m= achine is to generate an image with Buildroot. Version 2024.11.1 is tested at the= time -of writing and involves two steps. First run the following commands in the +of writing and involves three steps. First run the following commands in t= he toplevel directory of the Buildroot source tree: =20 .. code-block:: bash =20 - $ echo "BR2_TARGET_ROOTFS_CPIO=3Dy" >> configs/freescale_imx8mpevk_defco= nfig $ make freescale_imx8mpevk_defconfig $ make =20 Once finished successfully there is an ``output/image`` subfolder. Navigat= e into -it patch the device tree needs to be patched with the following commands w= hich +it and resize the SD card image to a power of two: + +.. code-block:: bash + + $ qemu-img resize sdcard.img 256M + +Finally, the device tree needs to be patched with the following commands w= hich will remove the ``cpu-idle-states`` properties from CPU nodes: =20 .. code-block:: bash @@ -54,5 +60,5 @@ Now that everything is prepared the newly built image can= be run in the QEMU -display none -serial null -serial stdio \ -kernel Image \ -dtb imx8mp-evk-patched.dtb \ - -initrd rootfs.cpio \ - -append "root=3D/dev/ram" + -append "root=3D/dev/mmcblk2p2" \ + -drive file=3Dsdcard.img,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmcblk2 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 26e24e99a1..349d55ca88 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -15,6 +15,7 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/sd/sdhci.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -28,6 +29,7 @@ enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_CPUS =3D 4, FSL_IMX8MP_NUM_IRQS =3D 160, FSL_IMX8MP_NUM_UARTS =3D 4, + FSL_IMX8MP_NUM_USDHCS =3D 3, }; =20 struct FslImx8mpState { @@ -39,6 +41,7 @@ struct FslImx8mpState { IMX8MPAnalogState analog; IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; + SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; }; =20 enum FslImx8mpMemoryRegions { @@ -184,6 +187,10 @@ enum FslImx8mpMemoryRegions { }; =20 enum FslImx8mpIrqs { + FSL_IMX8MP_USDHC1_IRQ =3D 22, + FSL_IMX8MP_USDHC2_IRQ =3D 23, + FSL_IMX8MP_USDHC3_IRQ =3D 24, + FSL_IMX8MP_UART1_IRQ =3D 26, FSL_IMX8MP_UART2_IRQ =3D 27, FSL_IMX8MP_UART3_IRQ =3D 28, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 32ca76c671..3e9fedf988 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -210,6 +210,11 @@ static void fsl_imx8mp_init(Object *obj) snprintf(name, NAME_SIZE, "uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } + + for (i =3D 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { + snprintf(name, NAME_SIZE, "usdhc%d", i + 1); + object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); + } } =20 static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) @@ -350,6 +355,28 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } =20 + /* USDHCs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } usdhc_table[FSL_IMX8MP_NUM_USDHCS] =3D { + { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC1].addr, FSL_IMX8MP_USDHC1= _IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC2].addr, FSL_IMX8MP_USDHC2= _IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC3].addr, FSL_IMX8MP_USDHC3= _IRQ }, + }; + + object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", + SDHCI_VENDOR_IMX, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].ad= dr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, + qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); + } + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -367,6 +394,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_RAM: case FSL_IMX8MP_SNVS_HP: case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4: + case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3: /* device implemented and treated above */ break; =20 diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index 2756d4c21c..27d9e9e8ee 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -11,6 +11,7 @@ #include "hw/arm/boot.h" #include "hw/arm/fsl-imx8mp.h" #include "hw/boards.h" +#include "hw/qdev-properties.h" #include "system/qtest.h" #include "qemu/error-report.h" #include "qapi/error.h" @@ -40,6 +41,23 @@ static void imx8mp_evk_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START, machine->ram); =20 + for (int i =3D 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { + BusState *bus; + DeviceState *carddev; + BlockBackend *blk; + DriveInfo *di =3D drive_get(IF_SD, i, 0); + + if (!di) { + continue; + } + + blk =3D blk_by_legacy_dinfo(di); + bus =3D qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); + carddev =3D qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_realize_and_unref(carddev, bus, &error_fatal); + } + if (!qtest_enabled()) { arm_load_kernel(&s->cpu[0], machine, &boot_info); } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0079c51734..7af8337354 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -583,6 +583,7 @@ config FSL_IMX8MP select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select SDHCI select UNIMP =20 config FSL_IMX8MP_EVK --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738661009; cv=none; d=zohomail.com; s=zohoarc; b=XdX8Nt+6ReA9KWNy50lnlRiiuZ9fm7NLWURLWNUf2ktjLN9r7QmoexePqghDuRGdmBjXlT0pdd5zGGZeJPRTb2JkyUsj3ddI+ZT0gJf/MNZXHnRLSQgqOJtzNXz6w51sz7IQFWNg3M0kMFveNQSl/KGkwgeHGgFzQKQNGudGnBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738661009; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pPk3Zz5sV2k7GKT+6nmWnPhElsFP+GWx5fqykFCdBYs=; b=LQrSH+JHCracAMboOdrXfKEBNMbpRr2pbHwofwsG+Rwd5YWAai0f2L7ve4JJlz1DC7ThVNdKJa2VhIDOnqQZCNT/QuS2mIWAky8V9wWhbRdeeIkOe0r1keXNnzfv3oFm+76ANDG5RCPfOwiqAcKCW62bN3vffdLmPqvhIV36wOA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173866100998537.18849586415979; Tue, 4 Feb 2025 01:23:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF7k-00050a-UN; Tue, 04 Feb 2025 04:21:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7i-0004xR-7x; Tue, 04 Feb 2025 04:21:38 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7f-00054i-PK; Tue, 04 Feb 2025 04:21:37 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-38dae70f5d9so139175f8f.1; Tue, 04 Feb 2025 01:21:34 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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Signed-off-by: Bernhard Beschow --- MAINTAINERS | 2 + docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 10 ++++ include/hw/pci-host/fsl_imx8m_phy.h | 27 +++++++++ hw/arm/fsl-imx8mp.c | 30 ++++++++++ hw/pci-host/fsl_imx8m_phy.c | 88 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 3 + hw/pci-host/Kconfig | 3 + hw/pci-host/meson.build | 1 + 9 files changed, 165 insertions(+) create mode 100644 include/hw/pci-host/fsl_imx8m_phy.h create mode 100644 hw/pci-host/fsl_imx8m_phy.c diff --git a/MAINTAINERS b/MAINTAINERS index 5b5b0d0bed..94af3d90e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -827,8 +827,10 @@ S: Maintained F: hw/arm/imx8mp-evk.c F: hw/arm/fsl-imx8mp.c F: hw/misc/imx8mp_*.c +F: hw/pci-host/fsl_imx8m_phy.c F: include/hw/arm/fsl-imx8mp.h F: include/hw/misc/imx8mp_*.h +F: include/hw/pci-host/fsl_imx8m_phy.h F: docs/system/arm/imx8mp-evk.rst =20 MPS2 / MPS3 diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 475c42d76a..39df695df7 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -14,6 +14,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * Generic Interrupt Controller (GICv3) * 4 UARTs * 3 USDHC Storage Controllers + * 1 Designware PCI Express Controller * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 349d55ca88..4c70c887a8 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -15,6 +15,8 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/pci-host/designware.h" +#include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "qom/object.h" #include "qemu/units.h" @@ -42,6 +44,8 @@ struct FslImx8mpState { IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; + DesignwarePCIEHost pcie; + FslImx8mPciePhyState pcie_phy; }; =20 enum FslImx8mpMemoryRegions { @@ -197,6 +201,12 @@ enum FslImx8mpIrqs { FSL_IMX8MP_UART4_IRQ =3D 29, FSL_IMX8MP_UART5_IRQ =3D 30, FSL_IMX8MP_UART6_IRQ =3D 16, + + FSL_IMX8MP_PCI_INTA_IRQ =3D 126, + FSL_IMX8MP_PCI_INTB_IRQ =3D 125, + FSL_IMX8MP_PCI_INTC_IRQ =3D 124, + FSL_IMX8MP_PCI_INTD_IRQ =3D 123, + FSL_IMX8MP_PCI_MSI_IRQ =3D 140, }; =20 #endif /* FSL_IMX8MP_H */ diff --git a/include/hw/pci-host/fsl_imx8m_phy.h b/include/hw/pci-host/fsl_= imx8m_phy.h new file mode 100644 index 0000000000..385a904fff --- /dev/null +++ b/include/hw/pci-host/fsl_imx8m_phy.h @@ -0,0 +1,27 @@ +/* + * i.MX8 PCIe PHY emulation + * + * Copyright (c) 2025 Bernhard Beschow + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_PCIHOST_FSLIMX8MPCIEPHY_H +#define HW_PCIHOST_FSLIMX8MPCIEPHY_H + +#include "hw/sysbus.h" +#include "qom/object.h" +#include "exec/memory.h" + +#define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy" + +OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mPciePhyState, FSL_IMX8M_PCIE_PHY) + +struct FslImx8mPciePhyState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint8_t data[0x800]; +}; + +#endif diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 3e9fedf988..faa6ada183 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -215,6 +215,10 @@ static void fsl_imx8mp_init(Object *obj) snprintf(name, NAME_SIZE, "usdhc%d", i + 1); object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } + + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); + object_initialize_child(obj, "pcie_phy", &s->pcie_phy, + TYPE_FSL_IMX8M_PCIE_PHY); } =20 static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) @@ -384,6 +388,30 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr); =20 + /* PCIe */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_PCIE1].addr); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTA_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTB_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTC_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTD_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_MSI_IRQ)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { switch (i) { @@ -391,6 +419,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_CCM: case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: + case FSL_IMX8MP_PCIE1: + case FSL_IMX8MP_PCIE_PHY1: case FSL_IMX8MP_RAM: case FSL_IMX8MP_SNVS_HP: case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4: diff --git a/hw/pci-host/fsl_imx8m_phy.c b/hw/pci-host/fsl_imx8m_phy.c new file mode 100644 index 0000000000..2f70e15c91 --- /dev/null +++ b/hw/pci-host/fsl_imx8m_phy.c @@ -0,0 +1,88 @@ +/* + * i.MX8 PCIe PHY emulation + * + * Copyright (c) 2025 Bernhard Beschow + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/pci-host/fsl_imx8m_phy.h" +#include "migration/vmstate.h" + +#define CMN_REG075 0x1d4 +#define ANA_PLL_LOCK_DONE BIT(1) +#define ANA_PLL_AFC_DONE BIT(0) + +static uint64_t fsl_imx8m_pcie_phy_read(void *opaque, hwaddr offset, + unsigned size) +{ + FslImx8mPciePhyState *s =3D opaque; + + if (offset =3D=3D CMN_REG075) { + return s->data[offset] | ANA_PLL_LOCK_DONE | ANA_PLL_AFC_DONE; + } + + return s->data[offset]; +} + +static void fsl_imx8m_pcie_phy_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + FslImx8mPciePhyState *s =3D opaque; + + s->data[offset] =3D value; +} + +static const MemoryRegionOps fsl_imx8m_pcie_phy_ops =3D { + .read =3D fsl_imx8m_pcie_phy_read, + .write =3D fsl_imx8m_pcie_phy_write, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void fsl_imx8m_pcie_phy_realize(DeviceState *dev, Error **errp) +{ + FslImx8mPciePhyState *s =3D FSL_IMX8M_PCIE_PHY(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &fsl_imx8m_pcie_phy_ops, s, + TYPE_FSL_IMX8M_PCIE_PHY, ARRAY_SIZE(s->data)); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static const VMStateDescription fsl_imx8m_pcie_phy_vmstate =3D { + .name =3D "fsl-imx8m-pcie-phy", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8_ARRAY(data, FslImx8mPciePhyState, + ARRAY_SIZE(((FslImx8mPciePhyState *)NULL)->dat= a)), + VMSTATE_END_OF_LIST() + } +}; + +static void fsl_imx8m_pcie_phy_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D fsl_imx8m_pcie_phy_realize; + dc->vmsd =3D &fsl_imx8m_pcie_phy_vmstate; +} + +static const TypeInfo fsl_imx8m_pcie_phy_types[] =3D { + { + .name =3D TYPE_FSL_IMX8M_PCIE_PHY, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(FslImx8mPciePhyState), + .class_init =3D fsl_imx8m_pcie_phy_class_init, + } +}; + +DEFINE_TYPES(fsl_imx8m_pcie_phy_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7af8337354..f1e140a29d 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -579,10 +579,13 @@ config FSL_IMX7 =20 config FSL_IMX8MP bool + imply PCI_DEVICES select ARM_GIC select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select PCI_EXPRESS_DESIGNWARE + select PCI_EXPRESS_FSL_IMX8M_PHY select SDHCI select UNIMP =20 diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index c91880b237..35c0415242 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -99,6 +99,9 @@ config ASTRO bool select PCI =20 +config PCI_EXPRESS_FSL_IMX8M_PHY + bool + config GT64120 bool select PCI diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index 3001e93a43..937a0f72ac 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -28,6 +28,7 @@ pci_ss.add(when: 'CONFIG_ARTICIA', if_true: files('artici= a.c')) pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c')) =20 # ARM devices +pci_ss.add(when: 'CONFIG_PCI_EXPRESS_FSL_IMX8M_PHY', if_true: files('fsl_i= mx8m_phy.c')) pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c')) =20 # HPPA devices --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 04 Feb 2025 01:21:31 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 09/18] hw/arm/fsl-imx8mp: Add GPIO controllers Date: Tue, 4 Feb 2025 10:21:03 +0100 Message-ID: <20250204092112.26957-10-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=shentey@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738660983587019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 14 +++++++++ hw/arm/fsl-imx8mp.c | 55 ++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 39df695df7..a89aad6f92 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -15,6 +15,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 4 UARTs * 3 USDHC Storage Controllers * 1 Designware PCI Express Controller + * 5 GPIO Controllers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 4c70c887a8..18ea52d083 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -11,6 +11,7 @@ =20 #include "cpu.h" #include "hw/char/imx_serial.h" +#include "hw/gpio/imx_gpio.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" @@ -29,6 +30,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP) =20 enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_CPUS =3D 4, + FSL_IMX8MP_NUM_GPIOS =3D 5, FSL_IMX8MP_NUM_IRQS =3D 160, FSL_IMX8MP_NUM_UARTS =3D 4, FSL_IMX8MP_NUM_USDHCS =3D 3, @@ -39,6 +41,7 @@ struct FslImx8mpState { =20 ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; GICv3State gic; + IMXGPIOState gpio[FSL_IMX8MP_NUM_GPIOS]; IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; @@ -202,6 +205,17 @@ enum FslImx8mpIrqs { FSL_IMX8MP_UART5_IRQ =3D 30, FSL_IMX8MP_UART6_IRQ =3D 16, =20 + FSL_IMX8MP_GPIO1_LOW_IRQ =3D 64, + FSL_IMX8MP_GPIO1_HIGH_IRQ =3D 65, + FSL_IMX8MP_GPIO2_LOW_IRQ =3D 66, + FSL_IMX8MP_GPIO2_HIGH_IRQ =3D 67, + FSL_IMX8MP_GPIO3_LOW_IRQ =3D 68, + FSL_IMX8MP_GPIO3_HIGH_IRQ =3D 69, + FSL_IMX8MP_GPIO4_LOW_IRQ =3D 70, + FSL_IMX8MP_GPIO4_HIGH_IRQ =3D 71, + FSL_IMX8MP_GPIO5_LOW_IRQ =3D 72, + FSL_IMX8MP_GPIO5_HIGH_IRQ =3D 73, + FSL_IMX8MP_PCI_INTA_IRQ =3D 126, FSL_IMX8MP_PCI_INTB_IRQ =3D 125, FSL_IMX8MP_PCI_INTC_IRQ =3D 124, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index faa6ada183..13910dc44a 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -211,6 +211,11 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { + snprintf(name, NAME_SIZE, "gpio%d", i + 1); + object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); + } + for (i =3D 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { snprintf(name, NAME_SIZE, "usdhc%d", i + 1); object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); @@ -359,6 +364,55 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } =20 + /* GPIOs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { + static const struct { + hwaddr addr; + unsigned int irq_low; + unsigned int irq_high; + } gpio_table[FSL_IMX8MP_NUM_GPIOS] =3D { + { + fsl_imx8mp_memmap[FSL_IMX8MP_GPIO1].addr, + FSL_IMX8MP_GPIO1_LOW_IRQ, + FSL_IMX8MP_GPIO1_HIGH_IRQ + }, + { + fsl_imx8mp_memmap[FSL_IMX8MP_GPIO2].addr, + FSL_IMX8MP_GPIO2_LOW_IRQ, + FSL_IMX8MP_GPIO2_HIGH_IRQ + }, + { + fsl_imx8mp_memmap[FSL_IMX8MP_GPIO3].addr, + FSL_IMX8MP_GPIO3_LOW_IRQ, + FSL_IMX8MP_GPIO3_HIGH_IRQ + }, + { + fsl_imx8mp_memmap[FSL_IMX8MP_GPIO4].addr, + FSL_IMX8MP_GPIO4_LOW_IRQ, + FSL_IMX8MP_GPIO4_HIGH_IRQ + }, + { + fsl_imx8mp_memmap[FSL_IMX8MP_GPIO5].addr, + FSL_IMX8MP_GPIO5_LOW_IRQ, + FSL_IMX8MP_GPIO5_HIGH_IRQ + }, + }; + + object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, + &error_abort); + object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", + true, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, + qdev_get_gpio_in(gicdev, gpio_table[i].irq_low)= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, + qdev_get_gpio_in(gicdev, gpio_table[i].irq_high= )); + } + /* USDHCs */ for (i =3D 0; i < FSL_IMX8MP_NUM_USDHCS; i++) { static const struct { @@ -419,6 +473,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_CCM: case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: + case FSL_IMX8MP_GPIO1 ... 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Tue, 04 Feb 2025 01:21:31 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 10/18] hw/arm/fsl-imx8mp: Add I2C controllers Date: Tue, 4 Feb 2025 10:21:04 +0100 Message-ID: <20250204092112.26957-11-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=shentey@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738661027591019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 11 +++++++++++ hw/arm/fsl-imx8mp.c | 29 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 ++ 4 files changed, 43 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index a89aad6f92..e63c5b7118 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -16,6 +16,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 3 USDHC Storage Controllers * 1 Designware PCI Express Controller * 5 GPIO Controllers + * 6 I2C Controllers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 18ea52d083..2590056627 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -12,6 +12,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/gpio/imx_gpio.h" +#include "hw/i2c/imx_i2c.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" @@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP) enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_CPUS =3D 4, FSL_IMX8MP_NUM_GPIOS =3D 5, + FSL_IMX8MP_NUM_I2CS =3D 6, FSL_IMX8MP_NUM_IRQS =3D 160, FSL_IMX8MP_NUM_UARTS =3D 4, FSL_IMX8MP_NUM_USDHCS =3D 3, @@ -45,6 +47,7 @@ struct FslImx8mpState { IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; + IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; DesignwarePCIEHost pcie; @@ -205,6 +208,11 @@ enum FslImx8mpIrqs { FSL_IMX8MP_UART5_IRQ =3D 30, FSL_IMX8MP_UART6_IRQ =3D 16, =20 + FSL_IMX8MP_I2C1_IRQ =3D 35, + FSL_IMX8MP_I2C2_IRQ =3D 36, + FSL_IMX8MP_I2C3_IRQ =3D 37, + FSL_IMX8MP_I2C4_IRQ =3D 38, + FSL_IMX8MP_GPIO1_LOW_IRQ =3D 64, FSL_IMX8MP_GPIO1_HIGH_IRQ =3D 65, FSL_IMX8MP_GPIO2_LOW_IRQ =3D 66, @@ -216,6 +224,9 @@ enum FslImx8mpIrqs { FSL_IMX8MP_GPIO5_LOW_IRQ =3D 72, FSL_IMX8MP_GPIO5_HIGH_IRQ =3D 73, =20 + FSL_IMX8MP_I2C5_IRQ =3D 76, + FSL_IMX8MP_I2C6_IRQ =3D 77, + FSL_IMX8MP_PCI_INTA_IRQ =3D 126, FSL_IMX8MP_PCI_INTB_IRQ =3D 125, FSL_IMX8MP_PCI_INTC_IRQ =3D 124, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 13910dc44a..1971c76aaa 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -211,6 +211,11 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MP_NUM_I2CS; i++) { + snprintf(name, NAME_SIZE, "i2c%d", i + 1); + object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); + } + for (i =3D 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { snprintf(name, NAME_SIZE, "gpio%d", i + 1); object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); @@ -364,6 +369,29 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } =20 + /* I2Cs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_I2CS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } i2c_table[FSL_IMX8MP_NUM_I2CS] =3D { + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C1].addr, FSL_IMX8MP_I2C1_IRQ= }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C2].addr, FSL_IMX8MP_I2C2_IRQ= }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C3].addr, FSL_IMX8MP_I2C3_IRQ= }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C4].addr, FSL_IMX8MP_I2C4_IRQ= }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C5].addr, FSL_IMX8MP_I2C5_IRQ= }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C6].addr, FSL_IMX8MP_I2C6_IRQ= }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, + qdev_get_gpio_in(gicdev, i2c_table[i].irq)); + } + /* GPIOs */ for (i =3D 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { static const struct { @@ -474,6 +502,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: + case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6: case FSL_IMX8MP_PCIE1: case FSL_IMX8MP_PCIE_PHY1: case FSL_IMX8MP_RAM: diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f1e140a29d..4a8695f22a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -579,11 +579,13 @@ config FSL_IMX7 =20 config FSL_IMX8MP bool + imply I2C_DEVICES imply PCI_DEVICES select ARM_GIC select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select IMX_I2C select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY select SDHCI --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738661032; cv=none; d=zohomail.com; s=zohoarc; b=jRX522p6fMB6zNsFh4Hq95+9vWnE33HGroC/U3R1Py0TbcPoUD/+H0CXrbPZktTxsAirKlGdrLWYbO0ZXse4PcTwMrHEI7Pmwaki8kXm5YWeMgIkueHQV+UtE66fHEuKHup1A6tpteZUu5swtKtshEAQUXnATHWswaBFKx0c428= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738661032; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hpJHicVT0FshEM/1uOuPzVqalFFdkNXqbR5+B54/jBU=; b=A/Pku3DWB2Gm5TYgrfLN0wg2NfxKxAlTTJuDPYWLZB03KRobWWXN7jrkTN3hjNftbh5/SFn8Zv6kkmULYiauUBB17sd6F9ZxiXA/2dtcssY6EJLBvsnLPXQyqDe2mRnLJJv1tHPOa/Wgt1wiLoS5951MxQLGiTftgCd+95jSHgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738661032110120.29598577274419; Tue, 4 Feb 2025 01:23:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF81-00057n-3s; Tue, 04 Feb 2025 04:21:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7i-0004xO-6w; Tue, 04 Feb 2025 04:21:38 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7g-000553-8f; Tue, 04 Feb 2025 04:21:37 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-436a03197b2so36472845e9.2; Tue, 04 Feb 2025 01:21:35 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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Tue, 04 Feb 2025 01:21:33 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers Date: Tue, 4 Feb 2025 10:21:05 +0100 Message-ID: <20250204092112.26957-12-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=shentey@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738661033608019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 8 ++++++++ hw/arm/fsl-imx8mp.c | 26 ++++++++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index e63c5b7118..eb7df2059f 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -17,6 +17,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 1 Designware PCI Express Controller * 5 GPIO Controllers * 6 I2C Controllers + * 3 SPI Controllers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 2590056627..296a87eb50 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -20,6 +20,7 @@ #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" +#include "hw/ssi/imx_spi.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP) =20 enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_CPUS =3D 4, + FSL_IMX8MP_NUM_ECSPIS =3D 3, FSL_IMX8MP_NUM_GPIOS =3D 5, FSL_IMX8MP_NUM_I2CS =3D 6, FSL_IMX8MP_NUM_IRQS =3D 160, @@ -47,6 +49,7 @@ struct FslImx8mpState { IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; + IMXSPIState spi[FSL_IMX8MP_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; @@ -208,6 +211,11 @@ enum FslImx8mpIrqs { FSL_IMX8MP_UART5_IRQ =3D 30, FSL_IMX8MP_UART6_IRQ =3D 16, =20 + FSL_IMX8MP_ECSPI1_IRQ =3D 31, + FSL_IMX8MP_ECSPI2_IRQ =3D 32, + FSL_IMX8MP_ECSPI3_IRQ =3D 33, + FSL_IMX8MP_ECSPI4_IRQ =3D 34, + FSL_IMX8MP_I2C1_IRQ =3D 35, FSL_IMX8MP_I2C2_IRQ =3D 36, FSL_IMX8MP_I2C3_IRQ =3D 37, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 1971c76aaa..fa39dfd2da 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -226,6 +226,11 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } =20 + for (i =3D 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) { + snprintf(name, NAME_SIZE, "spi%d", i + 1); + object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); + } + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -463,6 +468,26 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); } =20 + /* ECSPIs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } spi_table[FSL_IMX8MP_NUM_ECSPIS] =3D { + { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI1].addr, FSL_IMX8MP_ECSPI1= _IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI2].addr, FSL_IMX8MP_ECSPI2= _IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI3].addr, FSL_IMX8MP_ECSPI3= _IRQ }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(gicdev, spi_table[i].irq)); + } + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -502,6 +527,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: + case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3: case FSL_IMX8MP_I2C1 ... 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Tue, 04 Feb 2025 01:21:34 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 12/18] hw/arm/fsl-imx8mp: Add watchdog support Date: Tue, 4 Feb 2025 10:21:06 +0100 Message-ID: <20250204092112.26957-13-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738661045645019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 7 +++++++ hw/arm/fsl-imx8mp.c | 28 ++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + 4 files changed, 37 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index eb7df2059f..15514055b5 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -18,6 +18,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 5 GPIO Controllers * 6 I2C Controllers * 3 SPI Controllers + * 3 Watchdogs * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 296a87eb50..dfbdc6ac7f 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -21,6 +21,7 @@ #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" +#include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -38,6 +39,7 @@ enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_IRQS =3D 160, FSL_IMX8MP_NUM_UARTS =3D 4, FSL_IMX8MP_NUM_USDHCS =3D 3, + FSL_IMX8MP_NUM_WDTS =3D 3, }; =20 struct FslImx8mpState { @@ -53,6 +55,7 @@ struct FslImx8mpState { IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; + IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; }; @@ -235,6 +238,10 @@ enum FslImx8mpIrqs { FSL_IMX8MP_I2C5_IRQ =3D 76, FSL_IMX8MP_I2C6_IRQ =3D 77, =20 + FSL_IMX8MP_WDOG1_IRQ =3D 78, + FSL_IMX8MP_WDOG2_IRQ =3D 79, + FSL_IMX8MP_WDOG3_IRQ =3D 10, + FSL_IMX8MP_PCI_INTA_IRQ =3D 126, FSL_IMX8MP_PCI_INTB_IRQ =3D 125, FSL_IMX8MP_PCI_INTC_IRQ =3D 124, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index fa39dfd2da..6646f1c8b4 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -231,6 +231,11 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); } =20 + for (i =3D 0; i < FSL_IMX8MP_NUM_WDTS; i++) { + snprintf(name, NAME_SIZE, "wdt%d", i); + object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); + } + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -495,6 +500,28 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr); =20 + /* Watchdogs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_WDTS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } wdog_table[FSL_IMX8MP_NUM_WDTS] =3D { + { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG1].addr, FSL_IMX8MP_WDOG1_I= RQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG2].addr, FSL_IMX8MP_WDOG2_I= RQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG3].addr, FSL_IMX8MP_WDOG3_I= RQ }, + }; + + object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", + true, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, + qdev_get_gpio_in(gicdev, wdog_table[i].irq)); + } + /* PCIe */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { return; @@ -535,6 +562,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_SNVS_HP: case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4: case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3: + case FSL_IMX8MP_WDOG1 ... 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Tue, 04 Feb 2025 01:21:35 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 13/18] hw/arm/fsl-imx8mp: Implement gneral purpose timers Date: Tue, 4 Feb 2025 10:21:07 +0100 Message-ID: <20250204092112.26957-14-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=shentey@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738661055718019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 11 +++++++ include/hw/timer/imx_gpt.h | 1 + hw/arm/fsl-imx8mp.c | 53 ++++++++++++++++++++++++++++++++++ hw/timer/imx_gpt.c | 25 ++++++++++++++++ hw/arm/Kconfig | 1 + 6 files changed, 92 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 15514055b5..9293cabb85 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -19,6 +19,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 6 I2C Controllers * 3 SPI Controllers * 3 Watchdogs + * 6 General Purpose Timers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index dfbdc6ac7f..975887751b 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -17,10 +17,12 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/or-irq.h" #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" +#include "hw/timer/imx_gpt.h" #include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" @@ -35,6 +37,7 @@ enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_CPUS =3D 4, FSL_IMX8MP_NUM_ECSPIS =3D 3, FSL_IMX8MP_NUM_GPIOS =3D 5, + FSL_IMX8MP_NUM_GPTS =3D 6, FSL_IMX8MP_NUM_I2CS =3D 6, FSL_IMX8MP_NUM_IRQS =3D 160, FSL_IMX8MP_NUM_UARTS =3D 4, @@ -47,6 +50,7 @@ struct FslImx8mpState { =20 ARMCPU cpu[FSL_IMX8MP_NUM_CPUS]; GICv3State gic; + IMXGPTState gpt[FSL_IMX8MP_NUM_GPTS]; IMXGPIOState gpio[FSL_IMX8MP_NUM_GPIOS]; IMX8MPCCMState ccm; IMX8MPAnalogState analog; @@ -58,6 +62,7 @@ struct FslImx8mpState { IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; + OrIRQState gpt5_gpt6_irq; }; =20 enum FslImx8mpMemoryRegions { @@ -224,6 +229,12 @@ enum FslImx8mpIrqs { FSL_IMX8MP_I2C3_IRQ =3D 37, FSL_IMX8MP_I2C4_IRQ =3D 38, =20 + FSL_IMX8MP_GPT1_IRQ =3D 55, + FSL_IMX8MP_GPT2_IRQ =3D 54, + FSL_IMX8MP_GPT3_IRQ =3D 53, + FSL_IMX8MP_GPT4_IRQ =3D 52, + FSL_IMX8MP_GPT5_GPT6_IRQ =3D 51, + FSL_IMX8MP_GPIO1_LOW_IRQ =3D 64, FSL_IMX8MP_GPIO1_HIGH_IRQ =3D 65, FSL_IMX8MP_GPIO2_LOW_IRQ =3D 66, diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h index 5a1230da35..5488f7e4df 100644 --- a/include/hw/timer/imx_gpt.h +++ b/include/hw/timer/imx_gpt.h @@ -80,6 +80,7 @@ #define TYPE_IMX6_GPT "imx6.gpt" #define TYPE_IMX6UL_GPT "imx6ul.gpt" #define TYPE_IMX7_GPT "imx7.gpt" +#define TYPE_IMX8MP_GPT "imx8mp.gpt" =20 #define TYPE_IMX_GPT TYPE_IMX25_GPT =20 diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 6646f1c8b4..43395df628 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -211,6 +211,13 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MP_NUM_GPTS; i++) { + snprintf(name, NAME_SIZE, "gpt%d", i + 1); + object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX8MP_GPT); + } + object_initialize_child(obj, "gpt5-gpt6-irq", &s->gpt5_gpt6_irq, + TYPE_OR_IRQ); + for (i =3D 0; i < FSL_IMX8MP_NUM_I2CS; i++) { snprintf(name, NAME_SIZE, "i2c%d", i + 1); object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); @@ -379,6 +386,52 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } =20 + /* GPTs */ + object_property_set_int(OBJECT(&s->gpt5_gpt6_irq), "num-lines", 2, + &error_abort); + if (!qdev_realize(DEVICE(&s->gpt5_gpt6_irq), NULL, errp)) { + return; + } + + qdev_connect_gpio_out(DEVICE(&s->gpt5_gpt6_irq), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_GPT5_GPT6_IR= Q)); + + for (i =3D 0; i < FSL_IMX8MP_NUM_GPTS; i++) { + static const hwaddr gpt_addrs[FSL_IMX8MP_NUM_GPTS] =3D { + fsl_imx8mp_memmap[FSL_IMX8MP_GPT1].addr, + fsl_imx8mp_memmap[FSL_IMX8MP_GPT2].addr, + fsl_imx8mp_memmap[FSL_IMX8MP_GPT3].addr, + fsl_imx8mp_memmap[FSL_IMX8MP_GPT4].addr, + fsl_imx8mp_memmap[FSL_IMX8MP_GPT5].addr, + fsl_imx8mp_memmap[FSL_IMX8MP_GPT6].addr, + }; + + s->gpt[i].ccm =3D IMX_CCM(&s->ccm); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_addrs[i]); + + if (i < FSL_IMX8MP_NUM_GPTS - 2) { + static const unsigned int gpt_irqs[FSL_IMX8MP_NUM_GPTS - 2] = =3D { + FSL_IMX8MP_GPT1_IRQ, + FSL_IMX8MP_GPT2_IRQ, + FSL_IMX8MP_GPT3_IRQ, + FSL_IMX8MP_GPT4_IRQ, + }; + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, + qdev_get_gpio_in(gicdev, gpt_irqs[i])); + } else { + int irq =3D i - FSL_IMX8MP_NUM_GPTS + 2; + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, + qdev_get_gpio_in(DEVICE(&s->gpt5_gpt6_irq),= irq)); + } + } + /* I2Cs */ for (i =3D 0; i < FSL_IMX8MP_NUM_I2CS; i++) { static const struct { diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 11eca9fa4d..200a89225b 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -126,6 +126,17 @@ static const IMXClk imx7_gpt_clocks[] =3D { CLK_NONE, /* 111 not defined */ }; =20 +static const IMXClk imx8mp_gpt_clocks[] =3D { + CLK_NONE, /* 000 No clock source */ + CLK_IPG, /* 001 ipg_clk, 532MHz */ + CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ + CLK_EXT, /* 011 External clock */ + CLK_32k, /* 100 ipg_clk_32k */ + CLK_HIGH, /* 101 ipg_clk_16M */ + CLK_NONE, /* 110 not defined */ + CLK_NONE, /* 111 not defined */ +}; + /* Must be called from within ptimer_transaction_begin/commit block */ static void imx_gpt_set_freq(IMXGPTState *s) { @@ -552,6 +563,13 @@ static void imx7_gpt_init(Object *obj) s->clocks =3D imx7_gpt_clocks; } =20 +static void imx8mp_gpt_init(Object *obj) +{ + IMXGPTState *s =3D IMX_GPT(obj); + + s->clocks =3D imx8mp_gpt_clocks; +} + static const TypeInfo imx25_gpt_info =3D { .name =3D TYPE_IMX25_GPT, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -584,6 +602,12 @@ static const TypeInfo imx7_gpt_info =3D { .instance_init =3D imx7_gpt_init, }; =20 +static const TypeInfo imx8mp_gpt_info =3D { + .name =3D TYPE_IMX8MP_GPT, + .parent =3D TYPE_IMX25_GPT, + .instance_init =3D imx8mp_gpt_init, +}; + static void imx_gpt_register_types(void) { type_register_static(&imx25_gpt_info); @@ -591,6 +615,7 @@ static void imx_gpt_register_types(void) type_register_static(&imx6_gpt_info); type_register_static(&imx6ul_gpt_info); type_register_static(&imx7_gpt_info); + type_register_static(&imx8mp_gpt_info); } =20 type_init(imx_gpt_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 71102ac0a9..f2859f6a88 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -586,6 +586,7 @@ config FSL_IMX8MP select FSL_IMX8MP_CCM select IMX select IMX_I2C + select OR_IRQ select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY select SDHCI --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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There is no device model for the latter, so only add = the ENET one. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 8 ++++++++ hw/arm/fsl-imx8mp.c | 24 ++++++++++++++++++++++++ hw/arm/imx8mp-evk.c | 1 + hw/arm/Kconfig | 1 + 5 files changed, 35 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 9293cabb85..4109387b6e 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -15,6 +15,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 4 UARTs * 3 USDHC Storage Controllers * 1 Designware PCI Express Controller + * 1 Ethernet Controller * 5 GPIO Controllers * 6 I2C Controllers * 3 SPI Controllers diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 975887751b..e292c31a3d 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -17,6 +17,7 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/net/imx_fec.h" #include "hw/or-irq.h" #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" @@ -58,11 +59,15 @@ struct FslImx8mpState { IMXSPIState spi[FSL_IMX8MP_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; + IMXFECState enet; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; + + uint32_t phy_num; + bool phy_connected; }; =20 enum FslImx8mpMemoryRegions { @@ -253,6 +258,9 @@ enum FslImx8mpIrqs { FSL_IMX8MP_WDOG2_IRQ =3D 79, FSL_IMX8MP_WDOG3_IRQ =3D 10, =20 + FSL_IMX8MP_ENET1_MAC_IRQ =3D 118, + FSL_IMX6_ENET1_MAC_1588_IRQ =3D 121, + FSL_IMX8MP_PCI_INTA_IRQ =3D 126, FSL_IMX8MP_PCI_INTB_IRQ =3D 125, FSL_IMX8MP_PCI_INTC_IRQ =3D 124, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 43395df628..665123cf9c 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -243,6 +243,8 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); } =20 + object_initialize_child(obj, "eth0", &s->enet, TYPE_IMX_ENET); + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -546,6 +548,21 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, spi_table[i].irq)); } =20 + /* ENET1 */ + object_property_set_uint(OBJECT(&s->enet), "phy-num", s->phy_num, + &error_abort); + object_property_set_uint(OBJECT(&s->enet), "tx-ring-num", 3, &error_ab= ort); + qemu_configure_nic_device(DEVICE(&s->enet), true, NULL); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_ENET1].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_ENET1_MAC_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1, + qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IR= Q)); + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -608,6 +625,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3: + case FSL_IMX8MP_ENET1: case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6: case FSL_IMX8MP_PCIE1: case FSL_IMX8MP_PCIE_PHY1: @@ -628,10 +646,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Erro= r **errp) } } =20 +static const Property fsl_imx8mp_properties[] =3D { + DEFINE_PROP_UINT32("fec1-phy-num", FslImx8mpState, phy_num, 0), + DEFINE_PROP_BOOL("fec1-phy-connected", FslImx8mpState, phy_connected, = true), +}; + static void fsl_imx8mp_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 + device_class_set_props(dc, fsl_imx8mp_properties); dc->realize =3D fsl_imx8mp_realize; =20 dc->desc =3D "i.MX 8M Plus SoC"; diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index 27d9e9e8ee..e1a7892fd7 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -36,6 +36,7 @@ static void imx8mp_evk_init(MachineState *machine) =20 s =3D FSL_IMX8MP(object_new(TYPE_FSL_IMX8MP)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal); qdev_realize(DEVICE(s), NULL, &error_fatal); =20 memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f2859f6a88..7767a8725a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -585,6 +585,7 @@ config FSL_IMX8MP select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select IMX_FEC select IMX_I2C select OR_IRQ select PCI_EXPRESS_DESIGNWARE --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738661000; cv=none; d=zohomail.com; s=zohoarc; b=KdpOAKB4OgqFLimV9vz78HbRzVzWa4B+Wa8B5mGzyxcIugtorwEsI6x9nST0ftm2aI7SD87f+Iwy6mXZkIh1e3uljhoUjyKx9+hVlKR20deeASmtw6XYWx8hd0k6lJda16EoAr+Nh4WeXGzgqlSeGtqdvZyHqiOORRkOy3Wfmo8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738661000; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=42R2aSml+VKTf0LoVp/saQ6KjzZL2IBFiJZ1dmWdk5A=; b=OFJmBs/V/ul/r0enKk8easXF2ejPGBuls25H4kAUeVqMB1GNaU81pAFYVnyWdlh1/mPwct14T2p/l1hZv9gLBMSUN9Zd42R2iiwbBfPOH2i4MA3x6WOr7bkeCS0WhjJcZZkhe6S1CE/nzZGOe0ok9MZf8hsNAHlbbiS0F6twYUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738661000415634.3910470539425; Tue, 4 Feb 2025 01:23:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF85-0005aB-1m; Tue, 04 Feb 2025 04:22:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7m-00054P-FF; Tue, 04 Feb 2025 04:21:43 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7k-000566-AH; Tue, 04 Feb 2025 04:21:42 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-436202dd7f6so61910725e9.0; Tue, 04 Feb 2025 01:21:39 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 12 +++++++++++ hw/arm/fsl-imx8mp.c | 37 ++++++++++++++++++++++++++++++++-- hw/arm/Kconfig | 1 + 4 files changed, 49 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 4109387b6e..b3d657be10 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -16,6 +16,7 @@ The ``imx8mp-evk`` machine implements the following devic= es: * 3 USDHC Storage Controllers * 1 Designware PCI Express Controller * 1 Ethernet Controller + * 2 Designware USB 3 Controllers * 5 GPIO Controllers * 6 I2C Controllers * 3 SPI Controllers diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index e292c31a3d..5247e972b8 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -24,6 +24,7 @@ #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/timer/imx_gpt.h" +#include "hw/usb/hcd-dwc3.h" #include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" @@ -42,6 +43,7 @@ enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_I2CS =3D 6, FSL_IMX8MP_NUM_IRQS =3D 160, FSL_IMX8MP_NUM_UARTS =3D 4, + FSL_IMX8MP_NUM_USBS =3D 2, FSL_IMX8MP_NUM_USDHCS =3D 3, FSL_IMX8MP_NUM_WDTS =3D 3, }; @@ -62,6 +64,7 @@ struct FslImx8mpState { IMXFECState enet; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS]; + USBDWC3 usb[FSL_IMX8MP_NUM_USBS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; @@ -199,6 +202,12 @@ enum FslImx8mpMemoryRegions { FSL_IMX8MP_UART4, FSL_IMX8MP_USB1, FSL_IMX8MP_USB2, + FSL_IMX8MP_USB1_DEV, + FSL_IMX8MP_USB2_DEV, + FSL_IMX8MP_USB1_OTG, + FSL_IMX8MP_USB2_OTG, + FSL_IMX8MP_USB1_GLUE, + FSL_IMX8MP_USB2_GLUE, FSL_IMX8MP_USDHC1, FSL_IMX8MP_USDHC2, FSL_IMX8MP_USDHC3, @@ -234,6 +243,9 @@ enum FslImx8mpIrqs { FSL_IMX8MP_I2C3_IRQ =3D 37, FSL_IMX8MP_I2C4_IRQ =3D 38, =20 + FSL_IMX8MP_USB1_IRQ =3D 40, + FSL_IMX8MP_USB2_IRQ =3D 41, + FSL_IMX8MP_GPT1_IRQ =3D 55, FSL_IMX8MP_GPT2_IRQ =3D 54, FSL_IMX8MP_GPT3_IRQ =3D 53, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 665123cf9c..14d696957a 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -40,8 +40,14 @@ static const struct { [FSL_IMX8MP_VPU_VC8000E_ENCODER] =3D { 0x38320000, 2 * MiB, "vpu_vc800= 0e_encoder" }, [FSL_IMX8MP_VPU_G2_DECODER] =3D { 0x38310000, 2 * MiB, "vpu_g2_decoder= " }, [FSL_IMX8MP_VPU_G1_DECODER] =3D { 0x38300000, 2 * MiB, "vpu_g1_decoder= " }, - [FSL_IMX8MP_USB2] =3D { 0x38200000, 1 * MiB, "usb2" }, - [FSL_IMX8MP_USB1] =3D { 0x38100000, 1 * MiB, "usb1" }, + [FSL_IMX8MP_USB2_GLUE] =3D { 0x382f0000, 0x100, "usb2_glue" }, + [FSL_IMX8MP_USB2_OTG] =3D { 0x3820cc00, 0x100, "usb2_otg" }, + [FSL_IMX8MP_USB2_DEV] =3D { 0x3820c700, 0x500, "usb2_dev" }, + [FSL_IMX8MP_USB2] =3D { 0x38200000, 0xc700, "usb2" }, + [FSL_IMX8MP_USB1_GLUE] =3D { 0x381f0000, 0x100, "usb1_glue" }, + [FSL_IMX8MP_USB1_OTG] =3D { 0x3810cc00, 0x100, "usb1_otg" }, + [FSL_IMX8MP_USB1_DEV] =3D { 0x3810c700, 0x500, "usb1_dev" }, + [FSL_IMX8MP_USB1] =3D { 0x38100000, 0xc700, "usb1" }, [FSL_IMX8MP_GPU2D] =3D { 0x38008000, 32 * KiB, "gpu2d" }, [FSL_IMX8MP_GPU3D] =3D { 0x38000000, 32 * KiB, "gpu3d" }, [FSL_IMX8MP_QSPI1_RX_BUFFER] =3D { 0x34000000, 32 * MiB, "qspi1_rx_buf= fer" }, @@ -233,6 +239,11 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } =20 + for (i =3D 0; i < FSL_IMX8MP_NUM_USBS; i++) { + snprintf(name, NAME_SIZE, "usb%d", i); + object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3); + } + for (i =3D 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) { snprintf(name, NAME_SIZE, "spi%d", i + 1); object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); @@ -528,6 +539,27 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); } =20 + /* USBs */ + for (i =3D 0; i < FSL_IMX8MP_NUM_USBS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } usb_table[FSL_IMX8MP_NUM_USBS] =3D { + { fsl_imx8mp_memmap[FSL_IMX8MP_USB1].addr, FSL_IMX8MP_USB1_IRQ= }, + { fsl_imx8mp_memmap[FSL_IMX8MP_USB2].addr, FSL_IMX8MP_USB2_IRQ= }, + }; + + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p2", 1); + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p3", 1); + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0, + qdev_get_gpio_in(gicdev, usb_table[i].irq)); + } + /* ECSPIs */ for (i =3D 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) { static const struct { @@ -632,6 +664,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_RAM: case FSL_IMX8MP_SNVS_HP: case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4: + case FSL_IMX8MP_USB1 ... FSL_IMX8MP_USB2: case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3: case FSL_IMX8MP_WDOG1 ... FSL_IMX8MP_WDOG3: /* device implemented and treated above */ diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7767a8725a..6daa9c651f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -592,6 +592,7 @@ config FSL_IMX8MP select PCI_EXPRESS_FSL_IMX8M_PHY select SDHCI select UNIMP + select USB_DWC3 select WDT_IMX2 =20 config FSL_IMX8MP_EVK --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1738661079; cv=none; d=zohomail.com; s=zohoarc; b=fzMfA9QRAWST9LvdjVueEv27/XSjo7lJ2zOWcwv6pxBp/1yBtm6qpKaCLkdDogMPiP4EnMj5dDdO1QV2no0LwQvvlZT681m4ll0tJEu9wGxVYO5u1Xc7SSmZ7RHlKa4WlsFJH7NNuhW08SejRErHusFBbCEvGvYLwtTF1LWMVbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738661079; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iNwJL70TvJQ4/pz3SSQlqnGrmJeGd5p37x5US2YKiT0=; b=dqmlnHlfmPA+E9bD8/DahL4a1sgBUUNOCQ5UOue8ZQ1aa2zDDltq+cQL1c1q+PY67maWEwxeQwIGVk14dZxh6HIWAe92ujlJaOSrGohoLfXjQs1IWEsm9i5qrJzR327C2XR6tiPmpXsRFaQkJ+7Csn/H2Z1TLSMMvfbjGMTJTqU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738661079807838.9325697143489; Tue, 4 Feb 2025 01:24:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tfF82-0005OA-Ez; Tue, 04 Feb 2025 04:21:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tfF7n-00054X-6j; Tue, 04 Feb 2025 04:21:43 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tfF7l-00056H-0w; Tue, 04 Feb 2025 04:21:42 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-43622267b2eso53300305e9.0; Tue, 04 Feb 2025 01:21:40 -0800 (PST) Received: from Georg-PC.fritz.box (p200300faaf0043006a2cae69f03f1c85.dip0.t-ipconnect.de. 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Also, U-Boot calls into the ROM to determine the boot device. Whi= le we're not actually implementing this here, let's create the infrastructure = and add a dummy ROM with all zeros. This allows for implementing a ROM later wi= thout touching the source code and even allows for users to provide their own ROM= s. The imx8mp-boot.rom was created with `dd if=3D/dev/zero of=3Dimx8mp-boot.rom bs=3D1 count=3D258048`. Signed-off-by: Bernhard Beschow --- MAINTAINERS | 1 + include/hw/arm/fsl-imx8mp.h | 1 + hw/arm/fsl-imx8mp.c | 18 ++++++++++++++++++ pc-bios/imx8mp-boot.rom | Bin 0 -> 258048 bytes pc-bios/meson.build | 1 + 5 files changed, 21 insertions(+) create mode 100644 pc-bios/imx8mp-boot.rom diff --git a/MAINTAINERS b/MAINTAINERS index 94af3d90e4..ee837a3f6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -831,6 +831,7 @@ F: hw/pci-host/fsl_imx8m_phy.c F: include/hw/arm/fsl-imx8mp.h F: include/hw/misc/imx8mp_*.h F: include/hw/pci-host/fsl_imx8m_phy.h +F: pc-bios/imx8mp* F: docs/system/arm/imx8mp-evk.rst =20 MPS2 / MPS3 diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 5247e972b8..4dbe30f524 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -68,6 +68,7 @@ struct FslImx8mpState { DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; + MemoryRegion boot_rom; =20 uint32_t phy_num; bool phy_connected; diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 14d696957a..6439639110 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -9,12 +9,14 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/datadir.h" #include "exec/address-spaces.h" #include "hw/arm/bsa.h" #include "hw/arm/fsl-imx8mp.h" #include "hw/intc/arm_gicv3.h" #include "hw/misc/unimp.h" #include "hw/boards.h" +#include "hw/loader.h" #include "system/system.h" #include "target/arm/cpu-qom.h" #include "qapi/qmp/qlist.h" @@ -266,6 +268,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) MachineState *ms =3D MACHINE(qdev_get_machine()); FslImx8mpState *s =3D FSL_IMX8MP(dev); DeviceState *gicdev =3D DEVICE(&s->gic); + g_autofree char *filename =3D NULL; int i; =20 if (ms->smp.cpus > FSL_IMX8MP_NUM_CPUS) { @@ -648,10 +651,25 @@ static void fsl_imx8mp_realize(DeviceState *dev, Erro= r **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0, fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr); =20 + /* ROM memory */ + if (!memory_region_init_rom(&s->boot_rom, OBJECT(dev), + fsl_imx8mp_memmap[FSL_IMX8MP_BOOT_ROM].nam= e, + fsl_imx8mp_memmap[FSL_IMX8MP_BOOT_ROM].siz= e, + errp)) { + return; + } + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, "imx8mp-boot.rom"); + load_image_size(filename, memory_region_get_ram_ptr(&s->boot_rom), + memory_region_size(&s->boot_rom)); + memory_region_add_subregion(get_system_memory(), + fsl_imx8mp_memmap[FSL_IMX8MP_BOOT_ROM].add= r, + &s->boot_rom); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { switch (i) { case FSL_IMX8MP_ANA_PLL: + case FSL_IMX8MP_BOOT_ROM: case FSL_IMX8MP_CCM: case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: diff --git a/pc-bios/imx8mp-boot.rom b/pc-bios/imx8mp-boot.rom new file mode 100644 index 0000000000000000000000000000000000000000..5324b5eed200e723d048f8476e4= d96d45622fd4d GIT binary patch literal 258048 zcmeIuF#!Mo0K%a4Pi+Q&h(KY$fB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b* z1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA zz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEj zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r z3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@ z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VK zfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5 zV8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b* z1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwA zz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEj zFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r z3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@ z0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VK zfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5 zV8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM z7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b* z1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd z0RsjM7%*VKfB^#r3>YwAz<>b*1`HT5V8DO@0|pEjFkrxd0RsjM7%*VKfB^#r3>f$Z E2JkHa0RR91 literal 0 HcmV?d00001 diff --git a/pc-bios/meson.build b/pc-bios/meson.build index b68b29cc7d..64d3286fdd 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -60,6 +60,7 @@ blobs =3D [ 'efi-virtio.rom', 'efi-e1000e.rom', 'efi-vmxnet3.rom', + 'imx8mp-boot.rom', 'qemu-nsis.bmp', 'multiboot.bin', 'multiboot_dma.bin', --=20 2.48.1 From nobody Sat Feb 22 17:09:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 04 Feb 2025 01:21:39 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 17/18] hw/arm/fsl-imx8mp: Add on-chip RAM Date: Tue, 4 Feb 2025 10:21:11 +0100 Message-ID: <20250204092112.26957-18-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=shentey@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1738660933350019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- include/hw/arm/fsl-imx8mp.h | 1 + hw/arm/fsl-imx8mp.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 4dbe30f524..03f057c7db 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -69,6 +69,7 @@ struct FslImx8mpState { FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; MemoryRegion boot_rom; + MemoryRegion ocram; =20 uint32_t phy_num; bool phy_connected; diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 6439639110..e0dfe06e15 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -665,6 +665,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) fsl_imx8mp_memmap[FSL_IMX8MP_BOOT_ROM].add= r, &s->boot_rom); =20 + /* On-Chip RAM */ + if (!memory_region_init_ram(&s->ocram, NULL, "imx8mp.ocram", + fsl_imx8mp_memmap[FSL_IMX8MP_OCRAM].size, + errp)) { + return; + } + memory_region_add_subregion(get_system_memory(), + fsl_imx8mp_memmap[FSL_IMX8MP_OCRAM].addr, + &s->ocram); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) { switch (i) { @@ -677,6 +687,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3: case FSL_IMX8MP_ENET1: case FSL_IMX8MP_I2C1 ... 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Signed-off-by: Bernhard Beschow --- MAINTAINERS | 1 + hw/rtc/rs5c372.c | 227 ++++++++++++++++++++++++++++++++++++++++++++ hw/rtc/Kconfig | 5 + hw/rtc/meson.build | 1 + hw/rtc/trace-events | 4 + 5 files changed, 238 insertions(+) create mode 100644 hw/rtc/rs5c372.c diff --git a/MAINTAINERS b/MAINTAINERS index ee837a3f6e..d87435adba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -828,6 +828,7 @@ F: hw/arm/imx8mp-evk.c F: hw/arm/fsl-imx8mp.c F: hw/misc/imx8mp_*.c F: hw/pci-host/fsl_imx8m_phy.c +F: hw/rtc/rs5c372.c F: include/hw/arm/fsl-imx8mp.h F: include/hw/misc/imx8mp_*.h F: include/hw/pci-host/fsl_imx8m_phy.h diff --git a/hw/rtc/rs5c372.c b/hw/rtc/rs5c372.c new file mode 100644 index 0000000000..d300f93e13 --- /dev/null +++ b/hw/rtc/rs5c372.c @@ -0,0 +1,227 @@ +/* + * Ricoh RS5C372, R222x I2C RTC + * + * Copyright (c) 2025 Bernhard Beschow + * + * Based on hw/rtc/ds1338.c + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/i2c/i2c.h" +#include "migration/vmstate.h" +#include "qemu/bcd.h" +#include "qom/object.h" +#include "system/rtc.h" +#include "trace.h" + +#define NVRAM_SIZE 0x10 + +/* Flags definitions */ +#define SECONDS_CH 0x80 +#define HOURS_PM 0x20 +#define CTRL2_24 0x20 + +#define TYPE_RS5C372 "rs5c372" +OBJECT_DECLARE_SIMPLE_TYPE(RS5C372State, RS5C372) + +struct RS5C372State { + I2CSlave parent_obj; + + int64_t offset; + uint8_t wday_offset; + uint8_t nvram[NVRAM_SIZE]; + uint8_t ptr; + uint8_t tx_format; + bool addr_byte; +}; + +static const VMStateDescription vmstate_rs5c372 =3D { + .name =3D "rs5c372", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_I2C_SLAVE(parent_obj, RS5C372State), + VMSTATE_INT64(offset, RS5C372State), + VMSTATE_UINT8_V(wday_offset, RS5C372State, 2), + VMSTATE_UINT8_ARRAY(nvram, RS5C372State, NVRAM_SIZE), + VMSTATE_UINT8(ptr, RS5C372State), + VMSTATE_UINT8(tx_format, RS5C372State), + VMSTATE_BOOL(addr_byte, RS5C372State), + VMSTATE_END_OF_LIST() + } +}; + +static void capture_current_time(RS5C372State *s) +{ + /* + * Capture the current time into the secondary registers which will be + * actually read by the data transfer operation. + */ + struct tm now; + qemu_get_timedate(&now, s->offset); + s->nvram[0] =3D to_bcd(now.tm_sec); + s->nvram[1] =3D to_bcd(now.tm_min); + if (s->nvram[0xf] & CTRL2_24) { + s->nvram[2] =3D to_bcd(now.tm_hour); + } else { + int tmp =3D now.tm_hour; + if (tmp % 12 =3D=3D 0) { + tmp +=3D 12; + } + if (tmp <=3D 12) { + s->nvram[2] =3D to_bcd(tmp); + } else { + s->nvram[2] =3D HOURS_PM | to_bcd(tmp - 12); + } + } + s->nvram[3] =3D (now.tm_wday + s->wday_offset) % 7 + 1; + s->nvram[4] =3D to_bcd(now.tm_mday); + s->nvram[5] =3D to_bcd(now.tm_mon + 1); + s->nvram[6] =3D to_bcd(now.tm_year - 100); +} + +static void inc_regptr(RS5C372State *s) +{ + s->ptr =3D (s->ptr + 1) & (NVRAM_SIZE - 1); +} + +static int rs5c372_event(I2CSlave *i2c, enum i2c_event event) +{ + RS5C372State *s =3D RS5C372(i2c); + + switch (event) { + case I2C_START_RECV: + /* + * In h/w, capture happens on any START condition, not just a + * START_RECV, but there is no need to actually capture on + * START_SEND, because the guest can't get at that data + * without going through a START_RECV which would overwrite it. + */ + capture_current_time(s); + s->ptr =3D 0xf; + break; + case I2C_START_SEND: + s->addr_byte =3D true; + break; + default: + break; + } + + return 0; +} + +static uint8_t rs5c372_recv(I2CSlave *i2c) +{ + RS5C372State *s =3D RS5C372(i2c); + uint8_t res; + + res =3D s->nvram[s->ptr]; + + trace_rs5c372_recv(s->ptr, res); + + inc_regptr(s); + return res; +} + +static int rs5c372_send(I2CSlave *i2c, uint8_t data) +{ + RS5C372State *s =3D RS5C372(i2c); + + if (s->addr_byte) { + s->ptr =3D data >> 4; + s->tx_format =3D data & 0xf; + s->addr_byte =3D false; + return 0; + } + + trace_rs5c372_send(s->ptr, data); + + if (s->ptr < 7) { + /* Time register. */ + struct tm now; + qemu_get_timedate(&now, s->offset); + switch (s->ptr) { + case 0: + now.tm_sec =3D from_bcd(data & 0x7f); + break; + case 1: + now.tm_min =3D from_bcd(data & 0x7f); + break; + case 2: + if (s->nvram[0xf] & CTRL2_24) { + now.tm_hour =3D from_bcd(data & 0x3f); + } else { + int tmp =3D from_bcd(data & (HOURS_PM - 1)); + if (data & HOURS_PM) { + tmp +=3D 12; + } + if (tmp % 12 =3D=3D 0) { + tmp -=3D 12; + } + now.tm_hour =3D tmp; + } + break; + case 3: + { + /* + * The day field is supposed to contain a value in the ran= ge + * 1-7. Otherwise behavior is undefined. + */ + int user_wday =3D (data & 7) - 1; + s->wday_offset =3D (user_wday - now.tm_wday + 7) % 7; + } + break; + case 4: + now.tm_mday =3D from_bcd(data & 0x3f); + break; + case 5: + now.tm_mon =3D from_bcd(data & 0x1f) - 1; + break; + case 6: + now.tm_year =3D from_bcd(data) + 100; + break; + } + s->offset =3D qemu_timedate_diff(&now); + } else { + s->nvram[s->ptr] =3D data; + } + inc_regptr(s); + return 0; +} + +static void rs5c372_reset(DeviceState *dev) +{ + RS5C372State *s =3D RS5C372(dev); + + /* The clock is running and synchronized with the host */ + s->offset =3D 0; + s->wday_offset =3D 0; + memset(s->nvram, 0, NVRAM_SIZE); + s->ptr =3D 0; + s->addr_byte =3D false; +} + +static void rs5c372_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); + + k->event =3D rs5c372_event; + k->recv =3D rs5c372_recv; + k->send =3D rs5c372_send; + device_class_set_legacy_reset(dc, rs5c372_reset); + dc->vmsd =3D &vmstate_rs5c372; +} + +static const TypeInfo rs5c372_types[] =3D { + { + .name =3D TYPE_RS5C372, + .parent =3D TYPE_I2C_SLAVE, + .instance_size =3D sizeof(RS5C372State), + .class_init =3D rs5c372_class_init, + }, +}; + +DEFINE_TYPES(rs5c372_types) diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig index 2fe04ec1d0..315b0e4ecc 100644 --- a/hw/rtc/Kconfig +++ b/hw/rtc/Kconfig @@ -26,3 +26,8 @@ config GOLDFISH_RTC =20 config LS7A_RTC bool + +config RS5C372_RTC + bool + depends on I2C + default y if I2C_DEVICES diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build index 8ecc2d792c..6c87864dc0 100644 --- a/hw/rtc/meson.build +++ b/hw/rtc/meson.build @@ -13,3 +13,4 @@ system_ss.add(when: 'CONFIG_GOLDFISH_RTC', if_true: files= ('goldfish_rtc.c')) system_ss.add(when: 'CONFIG_LS7A_RTC', if_true: files('ls7a_rtc.c')) system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c= ')) system_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c')) +system_ss.add(when: 'CONFIG_RS5C372_RTC', if_true: files('rs5c372.c')) diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events index 8012afe102..b9f2852d35 100644 --- a/hw/rtc/trace-events +++ b/hw/rtc/trace-events @@ -35,3 +35,7 @@ m48txx_nvram_mem_write(uint32_t addr, uint32_t value) "me= m write addr:0x%04x val # goldfish_rtc.c goldfish_rtc_read(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " val= ue 0x%08" PRIx64 goldfish_rtc_write(uint64_t addr, uint64_t value) "addr 0x%02" PRIx64 " va= lue 0x%08" PRIx64 + +# rs5c372.c +rs5c372_recv(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] -> 0x%02" PRIx8 +rs5c372_send(uint32_t addr, uint8_t value) "[0x%" PRIx32 "] <- 0x%02" PRIx8 --=20 2.48.1