From nobody Wed Apr 16 15:37:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1738603915; cv=none; d=zohomail.com; s=zohoarc; b=RkRdwAjxRyClkHuiv6nWJww9eWDJG7rDmuT+iY7qL+mYkJ/urNRO5gXCgu6sVNkkUvTYuwNO0HDoeflIXwyQX4AX3LfSl89xHEg/CshZ+m0K0uj8rsM27Wg79dVU7L39KC9jLH3LWidifA7aawbLZVc/SnlJ1P7fSaD0oyKU2uo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1738603915; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=VOMcHwxHzo8e4jvXhaECTZv8xB1fqFEGqUtWeYzGiSs=; b=SIh8Ky/MjLbLHgZmTPnoSoNyR+1yJiJh6nIsirUJ+/35hUekjUX5r0+1ldwyw4dZLF9iJEwr0COlDzWoAgBqYghfK3f6h9NJBG+UKsjNj8h7dgGG+NEju5glmF7di6IXhttiQUdYtAd6EZHwuD93TxZTZGi2tQHuE/77TRsK5eg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738603915449780.7656785177142; Mon, 3 Feb 2025 09:31:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tf0IH-0008QH-3t; Mon, 03 Feb 2025 12:31:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tf0I2-0008EU-Pz; Mon, 03 Feb 2025 12:31:24 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tf0Hz-0005ZP-Kf; Mon, 03 Feb 2025 12:31:17 -0500 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Ymtkw1zCCz6L4yq; Tue, 4 Feb 2025 01:28:40 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id D32F61400CA; Tue, 4 Feb 2025 01:31:12 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.19.247) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 3 Feb 2025 18:31:12 +0100 To: , Fan Ni , Peter Maydell CC: , , , , Yuquan Wang , Itaru Kitayama , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v12 qemu 1/2] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Date: Mon, 3 Feb 2025 17:30:39 +0000 Message-ID: <20250203173040.145763-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203173040.145763-1-Jonathan.Cameron@huawei.com> References: <20250203173040.145763-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml500012.china.huawei.com (7.191.174.4) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738603917912019100 Content-Type: text/plain; charset="utf-8" Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. Note this is in a hole, so nothing should move. The CFMWs are placed above the extended memmap. Only create the CEDT table if cxl=3Don set for the machine. Signed-off-by: Jonathan Cameron --- include/hw/arm/virt.h | 4 +++ hw/arm/virt-acpi-build.c | 34 +++++++++++++++++++++++++ hw/arm/virt.c | 54 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c8e94e6aed..3e83d9e06b 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -36,6 +36,7 @@ #include "hw/arm/boot.h" #include "hw/arm/bsa.h" #include "hw/block/flash.h" +#include "hw/cxl/cxl.h" #include "system/kvm.h" #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" @@ -85,6 +86,7 @@ enum { /* indices of IO regions located after the RAM */ enum { VIRT_HIGH_GIC_REDIST2 =3D VIRT_LOWMEMMAP_LAST, + VIRT_CXL_HOST, VIRT_HIGH_PCIE_ECAM, VIRT_HIGH_PCIE_MMIO, }; @@ -146,6 +148,7 @@ struct VirtMachineState { bool secure; bool highmem; bool highmem_compact; + bool highmem_cxl; bool highmem_ecam; bool highmem_mmio; bool highmem_redists; @@ -180,6 +183,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + CXLState cxl_devices_state; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3ac8f8e178..339aa60ce5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -39,10 +39,12 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" +#include "hw/acpi/cxl.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/cxl/cxl.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -119,10 +121,29 @@ static void acpi_dsdt_add_flash(Aml *scope, const Mem= MapEntry *flash_memmap) aml_append(scope, dev); } =20 +static void build_acpi0017(Aml *table) +{ + Aml *dev, *scope, *method; + + scope =3D aml_scope("_SB"); + dev =3D aml_device("CXLM"); + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(dev, method); + build_cxl_dsm_method(dev); + + aml_append(scope, dev); + aml_append(table, scope); +} + static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, uint32_t irq, VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); + bool cxl_present =3D false; + PCIBus *bus =3D vms->bus; struct GPEXConfig cfg =3D { .mmio32 =3D memmap[VIRT_PCIE_MMIO], .pio =3D memmap[VIRT_PCIE_PIO], @@ -136,6 +157,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, } =20 acpi_dsdt_add_gpex(scope, &cfg); + QLIST_FOREACH(bus, &vms->bus->child, sibling) { + if (pci_bus_is_cxl(bus)) { + cxl_present =3D true; + } + } + if (cxl_present) { + build_acpi0017(scope); + } } =20 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, @@ -967,6 +996,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) } } =20 + if (vms->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + vms->oem_id, vms->oem_table_id, &vms->cxl_devices_s= tate); + } + if (ms->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, ms->nvdimms_state, ms->ram_slots, vms->oem_id, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99e0a68b6c..cc16a5750d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -56,6 +56,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "hw/pci-host/gpex.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/virtio/virtio-pci.h" #include "hw/core/sysbus-fdt.h" #include "hw/platform-bus.h" @@ -84,6 +85,8 @@ #include "hw/virtio/virtio-md-pci.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" =20 static GlobalProperty arm_virt_compat[] =3D { @@ -211,6 +214,7 @@ static const MemMapEntry base_memmap[] =3D { static MemMapEntry extended_memmap[] =3D { /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ [VIRT_HIGH_GIC_REDIST2] =3D { 0x0, 64 * MiB }, + [VIRT_CXL_HOST] =3D { 0x0, 64 * KiB * 16 }, /* 16 UID */ [VIRT_HIGH_PCIE_ECAM] =3D { 0x0, 256 * MiB }, /* Second PCIe window */ [VIRT_HIGH_PCIE_MMIO] =3D { 0x0, 512 * GiB }, @@ -1615,6 +1619,17 @@ static void create_pcie(VirtMachineState *vms) } } =20 +static void create_cxl_host_reg_region(VirtMachineState *vms) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &vms->cxl_devices_state.host_mr; + + memory_region_init(mr, OBJECT(vms), "cxl_host_reg", + vms->memmap[VIRT_CXL_HOST].size); + memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, m= r); + vms->highmem_cxl =3D true; +} + static void create_platform_bus(VirtMachineState *vms) { DeviceState *dev; @@ -1733,6 +1748,12 @@ void virt_machine_done(Notifier *notifier, void *dat= a) struct arm_boot_info *info =3D &vms->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 + cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, + &error_fatal); + + if (vms->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&vms->cxl_devices_state, &error_fatal); + } /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. This corresponds to a use case where @@ -1785,6 +1806,7 @@ static inline bool *virt_get_high_memmap_enabled(Virt= MachineState *vms, { bool *enabled_array[] =3D { &vms->highmem_redists, + &vms->highmem_cxl, &vms->highmem_ecam, &vms->highmem_mmio, }; @@ -1892,6 +1914,27 @@ static void virt_set_memmap(VirtMachineState *vms, i= nt pa_bits) if (device_memory_size > 0) { machine_memory_devices_init(ms, device_memory_base, device_memory_= size); } + + if (vms->cxl_devices_state.fixed_windows) { + GList *it; + + base =3D ROUND_UP(vms->highest_gpa + 1, 256 * MiB); + for (it =3D vms->cxl_devices_state.fixed_windows; it; it =3D it->n= ext) { + CXLFixedWindow *fw =3D it->data; + + if (base + fw->size <=3D BIT_ULL(pa_bits)) { + vms->highest_gpa =3D base + fw->size - 1; + } else { + error_report("CFMWS does not fit under PA limit"); + exit(EXIT_FAILURE); + } + + fw->base =3D base; + memory_region_init_io(&fw->mr, OBJECT(vms), &cfmws_ops, fw, + "cxl-fixed-memory-region", fw->size); + base +=3D fw->size; + } + } } =20 static VirtGICType finalize_gic_version_do(const char *accel_name, @@ -2346,6 +2389,15 @@ static void machvirt_init(MachineState *machine) memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, machine->ram); =20 + if (vms->cxl_devices_state.fixed_windows) { + GList *it; + for (it =3D vms->cxl_devices_state.fixed_windows; it; it =3D it->n= ext) { + CXLFixedWindow *fw =3D it->data; + + memory_region_add_subregion(sysmem, fw->base, &fw->mr); + } + } + virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 create_gic(vms, sysmem); @@ -2401,6 +2453,7 @@ static void machvirt_init(MachineState *machine) create_rtc(vms); =20 create_pcie(vms); + create_cxl_host_reg_region(vms); =20 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); @@ -3332,6 +3385,7 @@ static void virt_instance_init(Object *obj) =20 vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); + cxl_machine_init(obj, &vms->cxl_devices_state); } =20 static const TypeInfo virt_machine_info =3D { --=20 2.43.0