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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 69/69] target/arm: Sink fp_status and fpcr access into
do_fmlal*
Date: Sat, 1 Feb 2025 16:40:12 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Sink common code from the callers into do_fmlal
and do_fmlal_idx. Reorder the arguments to minimize
the re-sorting from the caller's arguments.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250129013857.135256-35-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/vec_helper.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index cc3586f44ac..986eaf8ffa4 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2125,9 +2125,13 @@ static uint64_t load4_f16(uint64_t *ptr, int is_q, i=
nt is_2)
* as there is not yet SVE versions that might use blocking.
*/
=20
-static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
- uint64_t negx, int negf, uint32_t desc, bool fz16)
+static void do_fmlal(float32 *d, void *vn, void *vm,
+ CPUARMState *env, uint32_t desc,
+ ARMFPStatusFlavour fpst_idx,
+ uint64_t negx, int negf)
{
+ float_status *fpst =3D &env->vfp.fp_status[fpst_idx];
+ bool fz16 =3D env->vfp.fpcr & FPCR_FZ16;
intptr_t i, oprsz =3D simd_oprsz(desc);
int is_2 =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
int is_q =3D oprsz =3D=3D 16;
@@ -2154,8 +2158,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void =
*vm,
bool is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1);
uint64_t negx =3D is_s ? 0x8000800080008000ull : 0;
=20
- do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_STD], negx, 0, desc,
- env->vfp.fpcr & FPCR_FZ16);
+ do_fmlal(vd, vn, vm, env, desc, FPST_STD, negx, 0);
}
=20
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
@@ -2172,8 +2175,7 @@ void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void =
*vm,
negx =3D 0x8000800080008000ull;
}
}
- do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_A64], negx, negf, desc,
- env->vfp.fpcr & FPCR_FZ16);
+ do_fmlal(vd, vn, vm, env, desc, FPST_A64, negx, negf);
}
=20
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
@@ -2205,9 +2207,13 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, v=
oid *vm, void *va,
}
}
=20
-static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fps=
t,
- uint64_t negx, int negf, uint32_t desc, bool fz16)
+static void do_fmlal_idx(float32 *d, void *vn, void *vm,
+ CPUARMState *env, uint32_t desc,
+ ARMFPStatusFlavour fpst_idx,
+ uint64_t negx, int negf)
{
+ float_status *fpst =3D &env->vfp.fp_status[fpst_idx];
+ bool fz16 =3D env->vfp.fpcr & FPCR_FZ16;
intptr_t i, oprsz =3D simd_oprsz(desc);
int is_2 =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
int index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3);
@@ -2235,8 +2241,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, v=
oid *vm,
bool is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1);
uint64_t negx =3D is_s ? 0x8000800080008000ull : 0;
=20
- do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_STD], negx, 0, desc,
- env->vfp.fpcr & FPCR_FZ16);
+ do_fmlal_idx(vd, vn, vm, env, desc, FPST_STD, negx, 0);
}
=20
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
@@ -2253,8 +2258,7 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, v=
oid *vm,
negx =3D 0x8000800080008000ull;
}
}
- do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_A64], negx, negf, de=
sc,
- env->vfp.fpcr & FPCR_FZ16);
+ do_fmlal_idx(vd, vn, vm, env, desc, FPST_A64, negx, negf);
}
=20
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
--=20
2.34.1