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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 61/69] target/arm: Remove ah_fp_status
Date: Sat, 1 Feb 2025 16:40:04 +0000
Message-Id: <20250201164012.1660228-62-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Replace with fp_status[FPST_AH].
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Message-id: 20250129013857.135256-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 3 +--
target/arm/cpu.c | 6 +++---
target/arm/vfp_helper.c | 6 +++---
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0f7d5d54305..5e3d952588a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -233,7 +233,7 @@ typedef struct NVICState NVICState;
* the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
* using a fixed value for it.
*
- * The ah_fp_status is needed because some insns have different
+ * FPST_AH is needed because some insns have different
* behaviour when FPCR.AH =3D=3D 1: they don't update cumulative
* exception flags, they act like FPCR.{FZ,FIZ} =3D {1,1} and
* they ignore FPCR.RMode. But they don't ignore FPCR.FZ16,
@@ -694,7 +694,6 @@ typedef struct CPUArchState {
float_status fp_status_a64;
float_status fp_status_f16_a32;
float_status fp_status_f16_a64;
- float_status ah_fp_status;
};
};
=20
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ffb2151de56..01a0428c6ed 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -556,9 +556,9 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t=
ype)
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]);
- arm_set_ah_fp_behaviours(&env->vfp.ah_fp_status);
- set_flush_to_zero(1, &env->vfp.ah_fp_status);
- set_flush_inputs_to_zero(1, &env->vfp.ah_fp_status);
+ arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]);
+ set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]);
+ set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]);
arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]);
=20
#ifndef CONFIG_USER_ONLY
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index b77f27d1811..09e707badeb 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -129,7 +129,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
a64_flags |=3D (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
& ~(float_flag_input_denormal_flushed | float_flag_input_denorma=
l_used));
/*
- * We do not merge in flags from ah_fp_status or FPST_AH_F16, because
+ * We do not merge in flags from FPST_AH or FPST_AH_F16, because
* they are used for insns that must not set the cumulative exception =
bits.
*/
=20
@@ -161,7 +161,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMStat=
e *env)
set_float_exception_flags(0, &env->vfp.fp_status_f16_a64);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]);
- set_float_exception_flags(0, &env->vfp.ah_fp_status);
+ set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH_F16]);
}
=20
@@ -236,7 +236,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint=
32_t val, uint32_t mask)
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64);
- set_default_nan_mode(dnan_enabled, &env->vfp.ah_fp_status);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16=
]);
}
if (changed & FPCR_AH) {
--=20
2.34.1