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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 50/69] target/arm: Handle FPCR.AH in SVE FMLSL (indexed)
Date: Sat, 1 Feb 2025 16:39:53 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=3D0
and by muladd flags when AH=3D1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need toa pass in the
FPCR.AH value via the SIMD data word.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250129013857.135256-32-richard.henderson@linaro.org
[PMM: commit message tweaked]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/vec_helper.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 5f0656f34ca..42bb43acd78 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2250,23 +2250,32 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, =
void *vm, void *va,
CPUARMState *env, uint32_t desc)
{
intptr_t i, j, oprsz =3D simd_oprsz(desc);
- uint16_t negn =3D extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
+ bool is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1);
intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(floa=
t16);
intptr_t idx =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(floa=
t16);
float_status *status =3D &env->vfp.fp_status_a64;
bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64);
+ int negx =3D 0, negf =3D 0;
+
+ if (is_s) {
+ if (env->vfp.fpcr & FPCR_AH) {
+ negf =3D float_muladd_negate_product;
+ } else {
+ negx =3D 0x8000;
+ }
+ }
=20
for (i =3D 0; i < oprsz; i +=3D 16) {
float16 mm_16 =3D *(float16 *)(vm + i + idx);
float32 mm =3D float16_to_float32_by_bits(mm_16, fz16);
=20
for (j =3D 0; j < 16; j +=3D sizeof(float32)) {
- float16 nn_16 =3D *(float16 *)(vn + H1_2(i + j + sel)) ^ negn;
+ float16 nn_16 =3D *(float16 *)(vn + H1_2(i + j + sel)) ^ negx;
float32 nn =3D float16_to_float32_by_bits(nn_16, fz16);
float32 aa =3D *(float32 *)(va + H1_4(i + j));
=20
*(float32 *)(vd + H1_4(i + j)) =3D
- float32_muladd(nn, mm, aa, 0, status);
+ float32_muladd(nn, mm, aa, negf, status);
}
}
}
--=20
2.34.1