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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 48/69] target/arm: Handle FPCR.AH in SVE FCMLA
Date: Sat, 1 Feb 2025 16:39:51 +0000
Message-Id: <20250201164012.1660228-49-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
The negation step in SVE FCMLA mustn't negate a NaN when FPCR.AH is
set. Use the same approach as we did for A64 FCMLA of passing in
FPCR.AH and using it to select whether to negate by XOR or by the
muladd negate_product flag.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250129013857.135256-28-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/sve_helper.c | 69 +++++++++++++++++++++-------------
target/arm/tcg/translate-sve.c | 2 +-
2 files changed, 43 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index c12b2600bd7..c206ca65ceb 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -5347,13 +5347,18 @@ void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, =
void *vm, void *va,
void *vg, float_status *status, uint32_t de=
sc)
{
intptr_t j, i =3D simd_oprsz(desc);
- unsigned rot =3D simd_data(desc);
- bool flip =3D rot & 1;
- float16 neg_imag, neg_real;
+ bool flip =3D extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 2, 1);
+ uint32_t negf_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t negf_real =3D flip ^ negf_imag;
+ float16 negx_imag, negx_real;
uint64_t *g =3D vg;
=20
- neg_imag =3D float16_set_sign(0, (rot & 2) !=3D 0);
- neg_real =3D float16_set_sign(0, rot =3D=3D 1 || rot =3D=3D 2);
+ /* With AH=3D0, use negx; with AH=3D1 use negf. */
+ negx_real =3D (negf_real & ~fpcr_ah) << 15;
+ negx_imag =3D (negf_imag & ~fpcr_ah) << 15;
+ negf_real =3D (negf_real & fpcr_ah ? float_muladd_negate_product : 0);
+ negf_imag =3D (negf_imag & fpcr_ah ? float_muladd_negate_product : 0);
=20
do {
uint64_t pg =3D g[(i - 1) >> 6];
@@ -5370,18 +5375,18 @@ void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, =
void *vm, void *va,
mi =3D *(float16 *)(vm + H1_2(j));
=20
e2 =3D (flip ? ni : nr);
- e1 =3D (flip ? mi : mr) ^ neg_real;
+ e1 =3D (flip ? mi : mr) ^ negx_real;
e4 =3D e2;
- e3 =3D (flip ? mr : mi) ^ neg_imag;
+ e3 =3D (flip ? mr : mi) ^ negx_imag;
=20
if (likely((pg >> (i & 63)) & 1)) {
d =3D *(float16 *)(va + H1_2(i));
- d =3D float16_muladd(e2, e1, d, 0, status);
+ d =3D float16_muladd(e2, e1, d, negf_real, status);
*(float16 *)(vd + H1_2(i)) =3D d;
}
if (likely((pg >> (j & 63)) & 1)) {
d =3D *(float16 *)(va + H1_2(j));
- d =3D float16_muladd(e4, e3, d, 0, status);
+ d =3D float16_muladd(e4, e3, d, negf_imag, status);
*(float16 *)(vd + H1_2(j)) =3D d;
}
} while (i & 63);
@@ -5392,13 +5397,18 @@ void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, =
void *vm, void *va,
void *vg, float_status *status, uint32_t de=
sc)
{
intptr_t j, i =3D simd_oprsz(desc);
- unsigned rot =3D simd_data(desc);
- bool flip =3D rot & 1;
- float32 neg_imag, neg_real;
+ bool flip =3D extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 2, 1);
+ uint32_t negf_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t negf_real =3D flip ^ negf_imag;
+ float32 negx_imag, negx_real;
uint64_t *g =3D vg;
=20
- neg_imag =3D float32_set_sign(0, (rot & 2) !=3D 0);
- neg_real =3D float32_set_sign(0, rot =3D=3D 1 || rot =3D=3D 2);
+ /* With AH=3D0, use negx; with AH=3D1 use negf. */
+ negx_real =3D (negf_real & ~fpcr_ah) << 31;
+ negx_imag =3D (negf_imag & ~fpcr_ah) << 31;
+ negf_real =3D (negf_real & fpcr_ah ? float_muladd_negate_product : 0);
+ negf_imag =3D (negf_imag & fpcr_ah ? float_muladd_negate_product : 0);
=20
do {
uint64_t pg =3D g[(i - 1) >> 6];
@@ -5415,18 +5425,18 @@ void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, =
void *vm, void *va,
mi =3D *(float32 *)(vm + H1_2(j));
=20
e2 =3D (flip ? ni : nr);
- e1 =3D (flip ? mi : mr) ^ neg_real;
+ e1 =3D (flip ? mi : mr) ^ negx_real;
e4 =3D e2;
- e3 =3D (flip ? mr : mi) ^ neg_imag;
+ e3 =3D (flip ? mr : mi) ^ negx_imag;
=20
if (likely((pg >> (i & 63)) & 1)) {
d =3D *(float32 *)(va + H1_2(i));
- d =3D float32_muladd(e2, e1, d, 0, status);
+ d =3D float32_muladd(e2, e1, d, negf_real, status);
*(float32 *)(vd + H1_2(i)) =3D d;
}
if (likely((pg >> (j & 63)) & 1)) {
d =3D *(float32 *)(va + H1_2(j));
- d =3D float32_muladd(e4, e3, d, 0, status);
+ d =3D float32_muladd(e4, e3, d, negf_imag, status);
*(float32 *)(vd + H1_2(j)) =3D d;
}
} while (i & 63);
@@ -5437,13 +5447,18 @@ void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, =
void *vm, void *va,
void *vg, float_status *status, uint32_t de=
sc)
{
intptr_t j, i =3D simd_oprsz(desc);
- unsigned rot =3D simd_data(desc);
- bool flip =3D rot & 1;
- float64 neg_imag, neg_real;
+ bool flip =3D extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 2, 1);
+ uint32_t negf_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t negf_real =3D flip ^ negf_imag;
+ float64 negx_imag, negx_real;
uint64_t *g =3D vg;
=20
- neg_imag =3D float64_set_sign(0, (rot & 2) !=3D 0);
- neg_real =3D float64_set_sign(0, rot =3D=3D 1 || rot =3D=3D 2);
+ /* With AH=3D0, use negx; with AH=3D1 use negf. */
+ negx_real =3D (uint64_t)(negf_real & ~fpcr_ah) << 63;
+ negx_imag =3D (uint64_t)(negf_imag & ~fpcr_ah) << 63;
+ negf_real =3D (negf_real & fpcr_ah ? float_muladd_negate_product : 0);
+ negf_imag =3D (negf_imag & fpcr_ah ? float_muladd_negate_product : 0);
=20
do {
uint64_t pg =3D g[(i - 1) >> 6];
@@ -5460,18 +5475,18 @@ void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, =
void *vm, void *va,
mi =3D *(float64 *)(vm + H1_2(j));
=20
e2 =3D (flip ? ni : nr);
- e1 =3D (flip ? mi : mr) ^ neg_real;
+ e1 =3D (flip ? mi : mr) ^ negx_real;
e4 =3D e2;
- e3 =3D (flip ? mr : mi) ^ neg_imag;
+ e3 =3D (flip ? mr : mi) ^ negx_imag;
=20
if (likely((pg >> (i & 63)) & 1)) {
d =3D *(float64 *)(va + H1_2(i));
- d =3D float64_muladd(e2, e1, d, 0, status);
+ d =3D float64_muladd(e2, e1, d, negf_real, status);
*(float64 *)(vd + H1_2(i)) =3D d;
}
if (likely((pg >> (j & 63)) & 1)) {
d =3D *(float64 *)(va + H1_2(j));
- d =3D float64_muladd(e4, e3, d, 0, status);
+ d =3D float64_muladd(e4, e3, d, negf_imag, status);
*(float64 *)(vd + H1_2(j)) =3D d;
}
} while (i & 63);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 410087c3fbd..6af94fedd0a 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -3955,7 +3955,7 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] =3D=
{
gen_helper_sve_fcmla_zpzzz_s, gen_helper_sve_fcmla_zpzzz_d,
};
TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz],
- a->rd, a->rn, a->rm, a->ra, a->pg, a->rot,
+ a->rd, a->rn, a->rm, a->ra, a->pg, a->rot | (s->fpcr_ah << 2),
a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] =3D {
--=20
2.34.1