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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 45/69] target/arm: Handle FPCR.AH in SVE FTMAD
Date: Sat, 1 Feb 2025 16:39:48 +0000
Message-Id: <20250201164012.1660228-46-peter.maydell@linaro.org>
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The negation step in the SVE FTMAD insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field,
so we can select the correct behaviour.
Because the operand is known to be negative, negating the operand
is the same as taking the absolute value. Defer this to the muladd
operation via flags, so that it happens after NaN detection, which
is correct for FPCR.AH.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Squsahed in RTH's patch to use muladd flags
---
target/arm/tcg/sve_helper.c | 42 ++++++++++++++++++++++++++--------
target/arm/tcg/translate-sve.c | 3 ++-
2 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index bf88bde8a31..c12b2600bd7 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -5134,16 +5134,24 @@ void HELPER(sve_ftmad_h)(void *vd, void *vn, void *=
vm,
0x3c00, 0xb800, 0x293a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
intptr_t i, opr_sz =3D simd_oprsz(desc) / sizeof(float16);
- intptr_t x =3D simd_data(desc);
+ intptr_t x =3D extract32(desc, SIMD_DATA_SHIFT, 3);
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 3, 1);
float16 *d =3D vd, *n =3D vn, *m =3D vm;
+
for (i =3D 0; i < opr_sz; i++) {
float16 mm =3D m[i];
intptr_t xx =3D x;
+ int flags =3D 0;
+
if (float16_is_neg(mm)) {
- mm =3D float16_abs(mm);
+ if (fpcr_ah) {
+ flags =3D float_muladd_negate_product;
+ } else {
+ mm =3D float16_abs(mm);
+ }
xx +=3D 8;
}
- d[i] =3D float16_muladd(n[i], mm, coeff[xx], 0, s);
+ d[i] =3D float16_muladd(n[i], mm, coeff[xx], flags, s);
}
}
=20
@@ -5157,16 +5165,24 @@ void HELPER(sve_ftmad_s)(void *vd, void *vn, void *=
vm,
0x37cd37cc, 0x00000000, 0x00000000, 0x00000000,
};
intptr_t i, opr_sz =3D simd_oprsz(desc) / sizeof(float32);
- intptr_t x =3D simd_data(desc);
+ intptr_t x =3D extract32(desc, SIMD_DATA_SHIFT, 3);
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 3, 1);
float32 *d =3D vd, *n =3D vn, *m =3D vm;
+
for (i =3D 0; i < opr_sz; i++) {
float32 mm =3D m[i];
intptr_t xx =3D x;
+ int flags =3D 0;
+
if (float32_is_neg(mm)) {
- mm =3D float32_abs(mm);
+ if (fpcr_ah) {
+ flags =3D float_muladd_negate_product;
+ } else {
+ mm =3D float32_abs(mm);
+ }
xx +=3D 8;
}
- d[i] =3D float32_muladd(n[i], mm, coeff[xx], 0, s);
+ d[i] =3D float32_muladd(n[i], mm, coeff[xx], flags, s);
}
}
=20
@@ -5184,16 +5200,24 @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *=
vm,
0x3e21ee96d2641b13ull, 0xbda8f76380fbb401ull,
};
intptr_t i, opr_sz =3D simd_oprsz(desc) / sizeof(float64);
- intptr_t x =3D simd_data(desc);
+ intptr_t x =3D extract32(desc, SIMD_DATA_SHIFT, 3);
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 3, 1);
float64 *d =3D vd, *n =3D vn, *m =3D vm;
+
for (i =3D 0; i < opr_sz; i++) {
float64 mm =3D m[i];
intptr_t xx =3D x;
+ int flags =3D 0;
+
if (float64_is_neg(mm)) {
- mm =3D float64_abs(mm);
+ if (fpcr_ah) {
+ flags =3D float_muladd_negate_product;
+ } else {
+ mm =3D float64_abs(mm);
+ }
xx +=3D 8;
}
- d[i] =3D float64_muladd(n[i], mm, coeff[xx], 0, s);
+ d[i] =3D float64_muladd(n[i], mm, coeff[xx], flags, s);
}
}
=20
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 2dd4605bb2f..410087c3fbd 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -3685,7 +3685,8 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] =3D=
{
gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
};
TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
- ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
+ ftmad_fns[a->esz], a->rd, a->rn, a->rm,
+ a->imm | (s->fpcr_ah << 3),
a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
/*
--=20
2.34.1