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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 44/69] target/arm: Handle FPCR.AH in SVE FTSSEL
Date: Sat, 1 Feb 2025 16:39:47 +0000
Message-Id: <20250201164012.1660228-45-peter.maydell@linaro.org>
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The negation step in the SVE FTSSEL insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: squashed in RTH's fix to use float*_maybe_ah_chs()
---
target/arm/tcg/sve_helper.c | 18 +++++++++++++++---
target/arm/tcg/translate-sve.c | 4 ++--
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index 90d4defc0d5..bf88bde8a31 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -2555,6 +2555,7 @@ void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_t=
desc)
void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz =3D simd_oprsz(desc) / 2;
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT, 1);
uint16_t *d =3D vd, *n =3D vn, *m =3D vm;
for (i =3D 0; i < opr_sz; i +=3D 1) {
uint16_t nn =3D n[i];
@@ -2562,13 +2563,17 @@ void HELPER(sve_ftssel_h)(void *vd, void *vn, void =
*vm, uint32_t desc)
if (mm & 1) {
nn =3D float16_one;
}
- d[i] =3D nn ^ (mm & 2) << 14;
+ if (mm & 2) {
+ nn =3D float16_maybe_ah_chs(nn, fpcr_ah);
+ }
+ d[i] =3D nn;
}
}
=20
void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz =3D simd_oprsz(desc) / 4;
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t *d =3D vd, *n =3D vn, *m =3D vm;
for (i =3D 0; i < opr_sz; i +=3D 1) {
uint32_t nn =3D n[i];
@@ -2576,13 +2581,17 @@ void HELPER(sve_ftssel_s)(void *vd, void *vn, void =
*vm, uint32_t desc)
if (mm & 1) {
nn =3D float32_one;
}
- d[i] =3D nn ^ (mm & 2) << 30;
+ if (mm & 2) {
+ nn =3D float32_maybe_ah_chs(nn, fpcr_ah);
+ }
+ d[i] =3D nn;
}
}
=20
void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz =3D simd_oprsz(desc) / 8;
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT, 1);
uint64_t *d =3D vd, *n =3D vn, *m =3D vm;
for (i =3D 0; i < opr_sz; i +=3D 1) {
uint64_t nn =3D n[i];
@@ -2590,7 +2599,10 @@ void HELPER(sve_ftssel_d)(void *vd, void *vn, void *=
vm, uint32_t desc)
if (mm & 1) {
nn =3D float64_one;
}
- d[i] =3D nn ^ (mm & 2) << 62;
+ if (mm & 2) {
+ nn =3D float64_maybe_ah_chs(nn, fpcr_ah);
+ }
+ d[i] =3D nn;
}
}
=20
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 17016854d87..2dd4605bb2f 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -1238,14 +1238,14 @@ static gen_helper_gvec_2 * const fexpa_fns[4] =3D {
gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
};
TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz,
- fexpa_fns[a->esz], a->rd, a->rn, 0)
+ fexpa_fns[a->esz], a->rd, a->rn, s->fpcr_ah)
=20
static gen_helper_gvec_3 * const ftssel_fns[4] =3D {
NULL, gen_helper_sve_ftssel_h,
gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
};
TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz,
- ftssel_fns[a->esz], a, 0)
+ ftssel_fns[a->esz], a, s->fpcr_ah)
=20
/*
*** SVE Predicate Logical Operations Group
--=20
2.34.1