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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 26/69] target/arm: Implement FPCR.AH semantics for FMAXV
and FMINV
Date: Sat, 1 Feb 2025 16:39:29 +0000
Message-Id: <20250201164012.1660228-27-peter.maydell@linaro.org>
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Implement the FPCR.AH semantics for FMAXV and FMINV. These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the _ah_ helper for the reduction step when
FPCR.AH =3D=3D 1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index cad9883f7dc..80a6562ed51 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7029,27 +7029,35 @@ static TCGv_i32 do_reduction_op(DisasContext *s, in=
t rn, MemOp esz,
}
=20
static bool do_fp_reduction(DisasContext *s, arg_qrr_e *a,
- NeonGenTwoSingleOpFn *fn)
+ NeonGenTwoSingleOpFn *fnormal,
+ NeonGenTwoSingleOpFn *fah)
{
if (fp_access_check(s)) {
MemOp esz =3D a->esz;
int elts =3D (a->q ? 16 : 8) >> esz;
TCGv_ptr fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : F=
PST_A64);
- TCGv_i32 res =3D do_reduction_op(s, a->rn, esz, 0, elts, fpst, fn);
+ TCGv_i32 res =3D do_reduction_op(s, a->rn, esz, 0, elts, fpst,
+ s->fpcr_ah ? fah : fnormal);
write_fp_sreg(s, a->rd, res);
}
return true;
}
=20
-TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_maxnum=
h)
-TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_minnum=
h)
-TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_maxh)
-TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a, gen_helper_vfp_minh)
+TRANS_FEAT(FMAXNMV_h, aa64_fp16, do_fp_reduction, a,
+ gen_helper_vfp_maxnumh, gen_helper_vfp_maxnumh)
+TRANS_FEAT(FMINNMV_h, aa64_fp16, do_fp_reduction, a,
+ gen_helper_vfp_minnumh, gen_helper_vfp_minnumh)
+TRANS_FEAT(FMAXV_h, aa64_fp16, do_fp_reduction, a,
+ gen_helper_vfp_maxh, gen_helper_vfp_ah_maxh)
+TRANS_FEAT(FMINV_h, aa64_fp16, do_fp_reduction, a,
+ gen_helper_vfp_minh, gen_helper_vfp_ah_minh)
=20
-TRANS(FMAXNMV_s, do_fp_reduction, a, gen_helper_vfp_maxnums)
-TRANS(FMINNMV_s, do_fp_reduction, a, gen_helper_vfp_minnums)
-TRANS(FMAXV_s, do_fp_reduction, a, gen_helper_vfp_maxs)
-TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins)
+TRANS(FMAXNMV_s, do_fp_reduction, a,
+ gen_helper_vfp_maxnums, gen_helper_vfp_maxnums)
+TRANS(FMINNMV_s, do_fp_reduction, a,
+ gen_helper_vfp_minnums, gen_helper_vfp_minnums)
+TRANS(FMAXV_s, do_fp_reduction, a, gen_helper_vfp_maxs, gen_helper_vfp_ah_=
maxs)
+TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins, gen_helper_vfp_ah_=
mins)
=20
/*
* Floating-point Immediate
--=20
2.34.1