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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 22/69] target/arm: Handle FPCR.NEP for FCVTXN (scalar)
Date: Sat, 1 Feb 2025 16:39:25 +0000
Message-Id: <20250201164012.1660228-23-peter.maydell@linaro.org>
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Unlike the other users of do_2misc_narrow_scalar(), FCVTXN (scalar)
is always double-to-single and must honour FPCR.NEP. Implement this
directly in a trans function rather than using
do_2misc_narrow_scalar().
We still need gen_fcvtxn_sd() and the f_scalar_fcvtxn[] array for
the FCVTXN (vector) insn, so we move those down in the file to
where they are used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 43 ++++++++++++++++++++++------------
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 35db806d0b7..73054b6137f 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9258,24 +9258,21 @@ static ArithOneOp * const f_scalar_uqxtn[] =3D {
};
TRANS(UQXTN_s, do_2misc_narrow_scalar, a, f_scalar_uqxtn)
=20
-static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
+static bool trans_FCVTXN_s(DisasContext *s, arg_rr_e *a)
{
- /*
- * 64 bit to 32 bit float conversion
- * with von Neumann rounding (round to odd)
- */
- TCGv_i32 tmp =3D tcg_temp_new_i32();
- gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_A64));
- tcg_gen_extu_i32_i64(d, tmp);
+ if (fp_access_check(s)) {
+ /*
+ * 64 bit to 32 bit float conversion
+ * with von Neumann rounding (round to odd)
+ */
+ TCGv_i64 src =3D read_fp_dreg(s, a->rn);
+ TCGv_i32 dst =3D tcg_temp_new_i32();
+ gen_helper_fcvtx_f64_to_f32(dst, src, fpstatus_ptr(FPST_A64));
+ write_fp_sreg_merging(s, a->rd, a->rd, dst);
+ }
+ return true;
}
=20
-static ArithOneOp * const f_scalar_fcvtxn[] =3D {
- NULL,
- NULL,
- gen_fcvtxn_sd,
-};
-TRANS(FCVTXN_s, do_2misc_narrow_scalar, a, f_scalar_fcvtxn)
-
#undef WRAP_ENV
=20
static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
@@ -9377,11 +9374,27 @@ static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
tcg_gen_extu_i32_i64(d, tmp);
}
=20
+static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
+{
+ /*
+ * 64 bit to 32 bit float conversion
+ * with von Neumann rounding (round to odd)
+ */
+ TCGv_i32 tmp =3D tcg_temp_new_i32();
+ gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_A64));
+ tcg_gen_extu_i32_i64(d, tmp);
+}
+
static ArithOneOp * const f_vector_fcvtn[] =3D {
NULL,
gen_fcvtn_hs,
gen_fcvtn_sd,
};
+static ArithOneOp * const f_scalar_fcvtxn[] =3D {
+ NULL,
+ NULL,
+ gen_fcvtxn_sd,
+};
TRANS(FCVTN_v, do_2misc_narrow_vector, a, f_vector_fcvtn)
TRANS(FCVTXN_v, do_2misc_narrow_vector, a, f_scalar_fcvtxn)
=20
--=20
2.34.1