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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 18/69] target/arm: Handle FPCR.NEP for BFCVT scalar
Date: Sat, 1 Feb 2025 16:39:21 +0000
Message-Id: <20250201164012.1660228-19-peter.maydell@linaro.org>
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Currently we implement BFCVT scalar via do_fp1_scalar(). This works
even though BFCVT is a narrowing operation from 32 to 16 bits,
because we can use write_fp_sreg() for float16. However, FPCR.NEP
support requires that we use write_fp_hreg_merging() for float16
outputs, so we can't continue to borrow the non-narrowing
do_fp1_scalar() function for this. Split out trans_BFCVT_s()
into its own implementation that honours FPCR.NEP.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 96696c342a9..030c5d99d78 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8582,10 +8582,27 @@ static const FPScalar1 f_scalar_frintx =3D {
};
TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1)
=20
-static const FPScalar1 f_scalar_bfcvt =3D {
- .gen_s =3D gen_helper_bfcvt,
-};
-TRANS_FEAT(BFCVT_s, aa64_bf16, do_fp1_scalar_ah, a, &f_scalar_bfcvt, -1)
+static bool trans_BFCVT_s(DisasContext *s, arg_rr_e *a)
+{
+ ARMFPStatusFlavour fpsttype =3D s->fpcr_ah ? FPST_AH : FPST_A64;
+ TCGv_i32 t32;
+ int check;
+
+ if (!dc_isar_feature(aa64_bf16, s)) {
+ return false;
+ }
+
+ check =3D fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <=3D 0) {
+ return check =3D=3D 0;
+ }
+
+ t32 =3D read_fp_sreg(s, a->rn);
+ gen_helper_bfcvt(t32, t32, fpstatus_ptr(fpsttype));
+ write_fp_hreg_merging(s, a->rd, a->rd, t32);
+ return true;
+}
=20
static const FPScalar1 f_scalar_frint32 =3D {
NULL,
--=20
2.34.1