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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 13/69] target/arm: Use FPST_FPCR_AH for BFCVT* insns
Date: Sat, 1 Feb 2025 16:39:16 +0000
Message-Id: <20250201164012.1660228-14-peter.maydell@linaro.org>
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When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2
* SVE BFCVT, BFCVTNT
so that they get the required behaviour changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 27 +++++++++++++++++++++------
target/arm/tcg/translate-sve.c | 6 ++++--
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index b01d05fe30e..bb32ccabf0e 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8514,7 +8514,7 @@ TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -=
1)
static const FPScalar1 f_scalar_bfcvt =3D {
.gen_s =3D gen_helper_bfcvt,
};
-TRANS_FEAT(BFCVT_s, aa64_bf16, do_fp1_scalar, a, &f_scalar_bfcvt, -1)
+TRANS_FEAT(BFCVT_s, aa64_bf16, do_fp1_scalar_ah, a, &f_scalar_bfcvt, -1)
=20
static const FPScalar1 f_scalar_frint32 =3D {
NULL,
@@ -9290,12 +9290,27 @@ static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n)
tcg_gen_extu_i32_i64(d, tmp);
}
=20
-static ArithOneOp * const f_vector_bfcvtn[] =3D {
- NULL,
- gen_bfcvtn_hs,
- NULL,
+static void gen_bfcvtn_ah_hs(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_ptr fpst =3D fpstatus_ptr(FPST_AH);
+ TCGv_i32 tmp =3D tcg_temp_new_i32();
+ gen_helper_bfcvt_pair(tmp, n, fpst);
+ tcg_gen_extu_i32_i64(d, tmp);
+}
+
+static ArithOneOp * const f_vector_bfcvtn[2][3] =3D {
+ {
+ NULL,
+ gen_bfcvtn_hs,
+ NULL,
+ }, {
+ NULL,
+ gen_bfcvtn_ah_hs,
+ NULL,
+ }
};
-TRANS_FEAT(BFCVTN_v, aa64_bf16, do_2misc_narrow_vector, a, f_vector_bfcvtn)
+TRANS_FEAT(BFCVTN_v, aa64_bf16, do_2misc_narrow_vector, a,
+ f_vector_bfcvtn[s->fpcr_ah])
=20
static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
{
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index c084bb58e7e..be2b5528ba0 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -3904,7 +3904,8 @@ TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16)
=20
TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_bfcvt, a, 0, FPST_A64)
+ gen_helper_sve_bfcvt, a, 0,
+ s->fpcr_ah ? FPST_AH : FPST_A64)
=20
TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
@@ -7054,7 +7055,8 @@ TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zp=
z,
gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64)
=20
TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_bfcvtnt, a, 0, FPST_A64)
+ gen_helper_sve_bfcvtnt, a, 0,
+ s->fpcr_ah ? FPST_AH : FPST_A64)
=20
TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64)
--=20
2.34.1