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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 09/69] target/arm: Adjust exception flag handling for AH =
1
Date: Sat, 1 Feb 2025 16:39:12 +0000
Message-Id: <20250201164012.1660228-10-peter.maydell@linaro.org>
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When FPCR.AH =3D 1, some of the cumulative exception flags in the FPSR
behave slightly differently for A64 operations:
* IDC is set when a denormal input is used without flushing
* IXC (Inexact) is set when an output denormal is flushed to zero
Update vfp_get_fpsr_from_host() to do this.
Note that because half-precision operations never set IDC, we now
need to add float_flag_input_denormal_used to the set we mask out of
fp_status_f16_a64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vfp_helper.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 62005e19524..57100e95378 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -78,7 +78,7 @@ static void arm_set_ah_fp_behaviours(float_status *s)
#ifdef CONFIG_TCG
=20
/* Convert host exception flags to vfp form. */
-static inline uint32_t vfp_exceptbits_from_host(int host_bits)
+static inline uint32_t vfp_exceptbits_from_host(int host_bits, bool ah)
{
uint32_t target_bits =3D 0;
=20
@@ -100,6 +100,16 @@ static inline uint32_t vfp_exceptbits_from_host(int ho=
st_bits)
if (host_bits & float_flag_input_denormal_flushed) {
target_bits |=3D FPSR_IDC;
}
+ /*
+ * With FPCR.AH, IDC is set when an input denormal is used,
+ * and flushing an output denormal to zero sets both IXC and UFC.
+ */
+ if (ah && (host_bits & float_flag_input_denormal_used)) {
+ target_bits |=3D FPSR_IDC;
+ }
+ if (ah && (host_bits & float_flag_output_denormal_flushed)) {
+ target_bits |=3D FPSR_IXC;
+ }
return target_bits;
}
=20
@@ -117,7 +127,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
=20
a64_flags |=3D get_float_exception_flags(&env->vfp.fp_status_a64);
a64_flags |=3D (get_float_exception_flags(&env->vfp.fp_status_f16_a64)
- & ~float_flag_input_denormal_flushed);
+ & ~(float_flag_input_denormal_flushed | float_flag_input_denorma=
l_used));
/*
* Flushing an input denormal *only* because FPCR.FIZ =3D=3D 1 does
* not set FPSR.IDC; if FPCR.FZ is also set then this takes
@@ -129,7 +139,8 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
if ((env->vfp.fpcr & (FPCR_FZ | FPCR_AH)) !=3D FPCR_FZ) {
a64_flags &=3D ~float_flag_input_denormal_flushed;
}
- return vfp_exceptbits_from_host(a32_flags | a64_flags);
+ return vfp_exceptbits_from_host(a64_flags, env->vfp.fpcr & FPCR_AH) |
+ vfp_exceptbits_from_host(a32_flags, false);
}
=20
static void vfp_clear_float_status_exc_flags(CPUARMState *env)
--=20
2.34.1