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From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Rob Herring <robh@kernel.org>, qemu-arm@nongnu.org,
Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair@alistair23.me>,
Igor Mitsyanko <i.mitsyanko@gmail.com>,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external
IRQs
Date: Thu, 30 Jan 2025 19:24:41 +0100
Message-ID: <20250130182441.40480-9-philmd@linaro.org>
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Implicit default values are often hard to figure out, better
be explicit. Now that all boards explicitly set the number of
GIC external IRQs, remove the default values (displaying an
error message if it is not set).
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
hw/cpu/a15mpcore.c | 13 ++++++-------
hw/cpu/a9mpcore.c | 14 +++++++-------
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 3b0897e54ee..372b615178f 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -58,6 +58,11 @@ static void a15mp_priv_realize(DeviceState *dev, Error *=
*errp)
bool has_el2 =3D false;
Object *cpuobj;
=20
+ if (!s->num_irq) {
+ error_setg(errp, "Property 'num-irq' not set");
+ return;
+ }
+
gicdev =3D DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
@@ -146,13 +151,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error=
**errp)
=20
static const Property a15mp_priv_properties[] =3D {
DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
- /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
- * IRQ lines (with another 32 internal). We default to 128+32, which
- * is the number provided by the Cortex-A15MP test chip in the
- * Versatile Express A15 development board.
- * Other boards may differ and should set this property appropriately.
- */
- DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
+ DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 0),
};
=20
static void a15mp_priv_class_init(ObjectClass *klass, void *data)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 9671585b5f9..c522f8d4b05 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -56,6 +56,12 @@ static void a9mp_priv_realize(DeviceState *dev, Error **=
errp)
CPUState *cpu0;
Object *cpuobj;
=20
+
+ if (!s->num_irq) {
+ error_setg(errp, "Property 'num-irq' not set");
+ return;
+ }
+
cpu0 =3D qemu_get_cpu(0);
cpuobj =3D OBJECT(cpu0);
if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9")=
)) {
@@ -160,13 +166,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error =
**errp)
=20
static const Property a9mp_priv_properties[] =3D {
DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
- /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
- * IRQ lines (with another 32 internal). We default to 64+32, which
- * is the number provided by the Cortex-A9MP test chip in the
- * Realview PBX-A9 and Versatile Express A9 development boards.
- * Other boards may differ and should set this property appropriately.
- */
- DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
+ DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 0),
};
=20
static void a9mp_priv_class_init(ObjectClass *klass, void *data)
--=20
2.47.1