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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH v2 04/34] target/arm: Rename FPST_FPCR_F16_A64 to FPST_A64_F16
Date: Tue, 28 Jan 2025 17:38:27 -0800
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
target/arm/tcg/translate.h | 8 ++---
target/arm/tcg/translate-a64.c | 44 +++++++++++------------
target/arm/tcg/translate-sve.c | 66 +++++++++++++++++-----------------
3 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index adf6eb8b91..cc753419ed 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -677,7 +677,7 @@ typedef enum ARMFPStatusFlavour {
FPST_A32,
FPST_A64,
FPST_A32_F16,
- FPST_FPCR_F16_A64,
+ FPST_A64_F16,
FPST_FPCR_AH,
FPST_FPCR_AH_F16,
FPST_STD,
@@ -698,7 +698,7 @@ typedef enum ARMFPStatusFlavour {
* for AArch64 non-FP16 operations controlled by the FPCR
* FPST_A32_F16
* for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to b=
e used
- * FPST_FPCR_F16_A64
+ * FPST_A64_F16
* for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to b=
e used
* FPST_FPCR_AH:
* for AArch64 operations which change behaviour when AH=3D1 (specifical=
ly,
@@ -726,7 +726,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour =
flavour)
case FPST_A32_F16:
offset =3D offsetof(CPUARMState, vfp.fp_status_f16_a32);
break;
- case FPST_FPCR_F16_A64:
+ case FPST_A64_F16:
offset =3D offsetof(CPUARMState, vfp.fp_status_f16_a64);
break;
case FPST_FPCR_AH:
@@ -757,7 +757,7 @@ static inline ARMFPStatusFlavour select_fpst(DisasConte=
xt *s, MemOp esz)
if (s->fpcr_ah) {
return esz =3D=3D MO_16 ? FPST_FPCR_AH_F16 : FPST_FPCR_AH;
} else {
- return esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64;
+ return esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64;
}
}
=20
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bf17ecca80..35d409685c 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5247,7 +5247,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e =
*a, const FPScalar *f,
{
return do_fp3_scalar_with_fpsttype(s, a, f, mergereg,
a->esz =3D=3D MO_16 ?
- FPST_FPCR_F16_A64 : FPST_A64);
+ FPST_A64_F16 : FPST_A64);
}
=20
static bool do_fp3_scalar_ah_2fn(DisasContext *s, arg_rrr_e *a,
@@ -5533,9 +5533,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a,
TCGv_i32 t0 =3D read_fp_hreg(s, a->rn);
TCGv_i32 t1 =3D tcg_constant_i32(0);
if (swap) {
- f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_FPCR_F16_A64));
+ f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_A64_F16));
} else {
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16_A64));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
}
write_fp_sreg(s, a->rd, t0);
}
@@ -5768,7 +5768,7 @@ static bool do_fp3_vector(DisasContext *s, arg_qrrr_e=
*a, int data,
{
return do_fp3_vector_with_fpsttype(s, a, data, fns,
a->esz =3D=3D MO_16 ?
- FPST_FPCR_F16_A64 :FPST_A64);
+ FPST_A64_F16 :FPST_A64);
}
=20
static bool do_fp3_vector_2fn(DisasContext *s, arg_qrrr_e *a, int data,
@@ -6174,7 +6174,7 @@ static bool trans_FCMLA_v(DisasContext *s, arg_FCMLA_=
v *a)
}
=20
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64,
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64,
a->rot, fn[a->esz]);
return true;
}
@@ -6566,7 +6566,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rr=
x_e *a, const FPScalar *f)
TCGv_i32 t1 =3D tcg_temp_new_i32();
=20
read_vec_element_i32(s, t1, a->rm, a->idx, MO_16);
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16_A64));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
write_fp_hreg_merging(s, a->rd, a->rn, t0);
}
break;
@@ -6624,7 +6624,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_r=
rx_e *a, bool neg)
gen_vfp_maybe_ah_negh(s, t1, t1);
}
gen_helper_advsimd_muladdh(t0, t1, t2, t0,
- fpstatus_ptr(FPST_FPCR_F16_A64));
+ fpstatus_ptr(FPST_A64_F16));
write_fp_hreg_merging(s, a->rd, a->rd, t0);
}
break;
@@ -6721,7 +6721,7 @@ static bool do_fp3_vector_idx(DisasContext *s, arg_qr=
rx_e *a,
}
=20
gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
- esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64,
+ esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64,
a->idx, fns[esz - 1]);
return true;
}
@@ -6755,7 +6755,7 @@ static bool do_fmla_vector_idx(DisasContext *s, arg_q=
rrx_e *a, bool neg)
}
=20
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
- esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64,
+ esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64,
(s->fpcr_ah << 5) | (a->idx << 1) | neg,
fns[esz - 1]);
return true;
@@ -6921,7 +6921,7 @@ static bool trans_FCMLA_vi(DisasContext *s, arg_FCMLA=
_vi *a)
}
if (fp_access_check(s)) {
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A=
64,
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64,
(a->idx << 2) | a->rot, fn);
}
return true;
@@ -6966,7 +6966,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_r=
r_e *a, const FPScalar *f)
=20
read_vec_element_i32(s, t0, a->rn, 0, MO_16);
read_vec_element_i32(s, t1, a->rn, 1, MO_16);
- f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16_A64));
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16));
write_fp_sreg(s, a->rd, t0);
}
break;
@@ -7148,7 +7148,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, =
bool neg_a, bool neg_n)
if (neg_n) {
gen_vfp_maybe_ah_negh(s, tn, tn);
}
- fpst =3D fpstatus_ptr(FPST_FPCR_F16_A64);
+ fpst =3D fpstatus_ptr(FPST_A64_F16);
gen_helper_advsimd_muladdh(ta, tn, tm, ta, fpst);
write_fp_hreg_merging(s, a->rd, a->ra, ta);
}
@@ -7243,7 +7243,7 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_=
e *a,
if (fp_access_check(s)) {
MemOp esz =3D a->esz;
int elts =3D (a->q ? 16 : 8) >> esz;
- TCGv_ptr fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16_A6=
4 : FPST_A64);
+ TCGv_ptr fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : F=
PST_A64);
TCGv_i32 res =3D do_reduction_op(s, a->rn, esz, 0, elts, fpst,
s->fpcr_ah ? fah : fnormal);
write_fp_sreg(s, a->rd, res);
@@ -7294,7 +7294,7 @@ static void handle_fp_compare(DisasContext *s, int si=
ze,
bool cmp_with_zero, bool signal_all_nans)
{
TCGv_i64 tcg_flags =3D tcg_temp_new_i64();
- TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16_A64 :=
FPST_A64);
+ TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_A64_F16 : FPST=
_A64);
=20
if (size =3D=3D MO_64) {
TCGv_i64 tcg_vn, tcg_vm;
@@ -8829,7 +8829,7 @@ static bool do_fp1_scalar(DisasContext *s, arg_rr_e *=
a,
{
return do_fp1_scalar_with_fpsttype(s, a, f, rmode,
a->esz =3D=3D MO_16 ?
- FPST_FPCR_F16_A64 : FPST_A64);
+ FPST_A64_F16 : FPST_A64);
}
=20
static bool do_fp1_scalar_ah(DisasContext *s, arg_rr_e *a,
@@ -8999,7 +8999,7 @@ static bool trans_FCVT_s_sh(DisasContext *s, arg_rr *=
a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn =3D read_fp_hreg(s, a->rn);
TCGv_i32 tcg_rd =3D tcg_temp_new_i32();
- TCGv_ptr tcg_fpst =3D fpstatus_ptr(FPST_FPCR_F16_A64);
+ TCGv_ptr tcg_fpst =3D fpstatus_ptr(FPST_A64_F16);
TCGv_i32 tcg_ahp =3D get_ahp_flag();
=20
gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
@@ -9013,7 +9013,7 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *=
a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn =3D read_fp_hreg(s, a->rn);
TCGv_i64 tcg_rd =3D tcg_temp_new_i64();
- TCGv_ptr tcg_fpst =3D fpstatus_ptr(FPST_FPCR_F16_A64);
+ TCGv_ptr tcg_fpst =3D fpstatus_ptr(FPST_A64_F16);
TCGv_i32 tcg_ahp =3D get_ahp_flag();
=20
gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
@@ -9029,7 +9029,7 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz=
, int rd, int shift,
TCGv_i32 tcg_shift, tcg_single;
TCGv_i64 tcg_double;
=20
- tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : F=
PST_A64);
+ tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A=
64);
tcg_shift =3D tcg_constant_i32(shift);
=20
switch (esz) {
@@ -9124,7 +9124,7 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out=
, MemOp esz,
TCGv_ptr tcg_fpstatus;
TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
=20
- tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : F=
PST_A64);
+ tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A=
64);
tcg_shift =3D tcg_constant_i32(shift);
tcg_rmode =3D gen_set_rmode(rmode, tcg_fpstatus);
=20
@@ -9773,7 +9773,7 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e =
*a,
return check =3D=3D 0;
}
=20
- fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A=
64);
+ fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64);
if (rmode >=3D 0) {
tcg_rmode =3D gen_set_rmode(rmode, fpst);
}
@@ -9847,7 +9847,7 @@ static bool do_gvec_op2_fpst(DisasContext *s, MemOp e=
sz, bool is_q,
gen_helper_gvec_2_ptr * const fns[3])
{
return do_gvec_op2_fpst_with_fpsttype(s, esz, is_q, rd, rn, data, fns,
- esz =3D=3D MO_16 ? FPST_FPCR_F16=
_A64 :
+ esz =3D=3D MO_16 ? FPST_A64_F16 :
FPST_A64);
}
=20
@@ -10024,7 +10024,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_=
e *a)
TCGv_i32 tcg_res[4];
TCGv_i32 ahp =3D get_ahp_flag();
=20
- fpst =3D fpstatus_ptr(FPST_FPCR_F16_A64);
+ fpst =3D fpstatus_ptr(FPST_A64_F16);
=20
for (pass =3D 0; pass < 4; pass++) {
tcg_res[pass] =3D tcg_temp_new_i32();
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 3cc678154a..3811316a2d 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -191,7 +191,7 @@ static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_=
helper_gvec_3_ptr *fn,
arg_rrr_esz *a, int data)
{
return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPS=
T_A64);
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64=
);
}
=20
static bool gen_gvec_fpst_ah_arg_zzz(DisasContext *s, gen_helper_gvec_3_pt=
r *fn,
@@ -404,7 +404,7 @@ static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen=
_helper_gvec_4_ptr *fn,
arg_rprr_esz *a)
{
return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FP=
ST_A64);
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A6=
4);
}
=20
/* Invoke a vector expander on two Zregs and an immediate. */
@@ -3534,7 +3534,7 @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_es=
z *a, bool sub)
};
return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
(s->fpcr_ah << 5) | (a->index << 1) | sub,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FP=
ST_A64);
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A6=
4);
}
=20
TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false)
@@ -3550,7 +3550,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] =
=3D {
};
TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
/*
*** SVE Floating Point Fast Reduction Group
@@ -3583,7 +3583,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
=20
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
- status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST=
_A64);
+ status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64);
=20
fn(temp, t_zn, t_pg, status, t_desc);
=20
@@ -3659,7 +3659,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a,
if (sve_access_check(s)) {
unsigned vsz =3D vec_full_reg_size(s);
TCGv_ptr status =3D
- fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A6=
4);
+ fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64);
=20
tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
@@ -3696,7 +3696,7 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] =3D=
{
TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
ftmad_fns[a->esz], a->rd, a->rn, a->rm,
a->imm | (s->fpcr_ah << 3),
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
/*
*** SVE Floating Point Accumulating Reduction Group
@@ -3729,7 +3729,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz=
*a)
t_pg =3D tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
- t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST=
_A64);
+ t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64);
t_desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0));
=20
fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
@@ -3829,7 +3829,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int=
zn, int pg, bool is_fp16,
tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn));
tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
=20
- status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16_A64 : FPST_A64);
+ status =3D fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64);
desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0));
fn(t_zd, t_zn, t_pg, scalar, status, desc);
}
@@ -3902,7 +3902,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *=
a,
}
if (sve_access_check(s)) {
unsigned vsz =3D vec_full_reg_size(s);
- TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F=
16_A64 : FPST_A64);
+ TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F1=
6 : FPST_A64);
tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
@@ -3935,7 +3935,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] =3D {
};
TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz],
a->rd, a->rn, a->rm, a->pg, a->rot | (s->fpcr_ah << 1),
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
#define DO_FMLA(NAME, name, ah_name) \
static gen_helper_gvec_5_ptr * const name##_fns[4] =3D { \
@@ -3949,7 +3949,7 @@ TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd=
_fns[a->esz],
TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_zzzzp, \
s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz], \
a->rd, a->rn, a->rm, a->ra, a->pg, 0, \
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
/* We don't need an ah_fmla_zpzzz because fmla doesn't negate anything */
DO_FMLA(FMLA_zpzzz, fmla_zpzzz, fmla_zpzzz)
@@ -3965,14 +3965,14 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] =
=3D {
};
TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz],
a->rd, a->rn, a->rm, a->ra, a->pg, a->rot,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] =3D {
NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL
};
TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz],
a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot,
- a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
/*
*** SVE Floating Point Unary Operations Predicated Group
@@ -3981,7 +3981,7 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, =
fcmla_idx_fns[a->esz],
TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_sh, a, 0, FPST_A64)
TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16)
=20
TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
gen_helper_sve_bfcvt, a, 0,
@@ -3990,24 +3990,24 @@ TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_=
zpz,
TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_ds, a, 0, FPST_A64)
TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvt_sd, a, 0, FPST_A64)
=20
TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16)
TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16)
=20
TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64)
@@ -4034,7 +4034,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] =3D {
gen_helper_sve_frint_d
};
TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
- a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
static gen_helper_gvec_3_ptr * const frintx_fns[] =3D {
NULL,
@@ -4043,7 +4043,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] =3D=
{
gen_helper_sve_frintx_d
};
TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
- a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64);
+ a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64);
=20
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
@@ -4060,7 +4060,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_es=
z *a,
}
=20
vsz =3D vec_full_reg_size(s);
- status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST=
_A64);
+ status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64);
tmode =3D gen_set_rmode(mode, status);
=20
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
@@ -4095,14 +4095,14 @@ static gen_helper_gvec_3_ptr * const fsqrt_fns[] =
=3D {
gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
};
TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
- a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16)
TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16)
=20
TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_scvt_ss, a, 0, FPST_A64)
@@ -4115,11 +4115,11 @@ TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zp=
z,
gen_helper_sve_scvt_dd, a, 0, FPST_A64)
=20
TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16)
TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16)
TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
- gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16_A64)
+ gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16)
=20
TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
gen_helper_sve_ucvt_ss, a, 0, FPST_A64)
@@ -7153,7 +7153,7 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] =3D {
gen_helper_flogb_s, gen_helper_flogb_d
};
TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
- a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16_A64 : FPST_A64)
+ a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64)
=20
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool=
sel)
{
--=20
2.43.0