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Tue, 28 Jan 2025 17:39:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 03/34] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16 Date: Tue, 28 Jan 2025 17:38:26 -0800 Message-ID: <20250129013857.135256-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129013857.135256-1-richard.henderson@linaro.org> References: <20250129013857.135256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1738115104474019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate.h | 6 +++--- target/arm/tcg/translate-vfp.c | 24 ++++++++++++------------ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 2edb707b85..adf6eb8b91 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -676,7 +676,7 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const T= ranslationBlock *tb) typedef enum ARMFPStatusFlavour { FPST_A32, FPST_A64, - FPST_FPCR_F16_A32, + FPST_A32_F16, FPST_FPCR_F16_A64, FPST_FPCR_AH, FPST_FPCR_AH_F16, @@ -696,7 +696,7 @@ typedef enum ARMFPStatusFlavour { * for AArch32 non-FP16 operations controlled by the FPCR * FPST_A64 * for AArch64 non-FP16 operations controlled by the FPCR - * FPST_FPCR_F16_A32 + * FPST_A32_F16 * for AArch32 operations controlled by the FPCR where FPCR.FZ16 is to b= e used * FPST_FPCR_F16_A64 * for AArch64 operations controlled by the FPCR where FPCR.FZ16 is to b= e used @@ -723,7 +723,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour = flavour) case FPST_A64: offset =3D offsetof(CPUARMState, vfp.fp_status_a64); break; - case FPST_FPCR_F16_A32: + case FPST_A32_F16: offset =3D offsetof(CPUARMState, vfp.fp_status_f16_a32); break; case FPST_FPCR_F16_A64: diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 4cc12a407b..8d9d1ab877 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -460,7 +460,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) } =20 if (sz =3D=3D 1) { - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); } else { fpst =3D fpstatus_ptr(FPST_A32); } @@ -527,7 +527,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } =20 if (sz =3D=3D 1) { - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); } else { fpst =3D fpstatus_ptr(FPST_A32); } @@ -1433,7 +1433,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpS= PFn *fn, /* * Do a half-precision operation. Functionally this is * the same as do_vfp_3op_sp(), except: - * - it uses the FPST_FPCR_F16_A32 + * - it uses the FPST_A32_F16 * - it doesn't need the VFP vector handling (fp16 is a * v8 feature, and in v8 VFP vectors don't exist) * - it does the aa32_fp16_arith feature test @@ -1456,7 +1456,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpS= PFn *fn, f0 =3D tcg_temp_new_i32(); f1 =3D tcg_temp_new_i32(); fd =3D tcg_temp_new_i32(); - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); =20 vfp_load_reg16(f0, vn); vfp_load_reg16(f1, vm); @@ -2122,7 +2122,7 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_vfp_negh(vd, vd); } - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); vfp_store_reg32(vd, a->vd); return true; @@ -2424,7 +2424,7 @@ DO_VFP_2OP(VNEG, dp, gen_vfp_negd, aa32_fpdp_v2) =20 static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) { - gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_FPCR_F16_A32)); + gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_A32_F16)); } =20 static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) @@ -2706,7 +2706,7 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRIN= TR_sp *a) =20 tmp =3D tcg_temp_new_i32(); vfp_load_reg16(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); gen_helper_rinth(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2779,7 +2779,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRIN= TZ_sp *a) =20 tmp =3D tcg_temp_new_i32(); vfp_load_reg16(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); tcg_rmode =3D gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rinth(tmp, tmp, fpst); gen_restore_rmode(tcg_rmode, fpst); @@ -2859,7 +2859,7 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRIN= TX_sp *a) =20 tmp =3D tcg_temp_new_i32(); vfp_load_reg16(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); gen_helper_rinth_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2983,7 +2983,7 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VC= VT_int_sp *a) =20 vm =3D tcg_temp_new_i32(); vfp_load_reg32(vm, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); if (a->s) { /* i32 -> f16 */ gen_helper_vfp_sitoh(vm, vm, fpst); @@ -3105,7 +3105,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC= VT_fix_sp *a) vd =3D tcg_temp_new_i32(); vfp_load_reg32(vd, a->vd); =20 - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); shift =3D tcg_constant_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -3273,7 +3273,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VC= VT_sp_int *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR_F16_A32); + fpst =3D fpstatus_ptr(FPST_A32_F16); vm =3D tcg_temp_new_i32(); vfp_load_reg16(vm, a->vm); =20 --=20 2.43.0