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Tue, 28 Jan 2025 17:39:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 32/34] target/arm: Handle FPCR.AH in sve2_fmlal_zzzw_s Date: Tue, 28 Jan 2025 17:38:55 -0800 Message-ID: <20250129013857.135256-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129013857.135256-1-richard.henderson@linaro.org> References: <20250129013857.135256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1738114956197019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index c716bd774a..bae98a34b8 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2180,19 +2180,28 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, = void *vm, void *va, CPUARMState *env, uint32_t desc) { intptr_t i, oprsz =3D simd_oprsz(desc); - uint16_t negn =3D extract32(desc, SIMD_DATA_SHIFT, 1) << 15; + bool is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(floa= t16); float_status *status =3D &env->vfp.fp_status[FPST_A64]; bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F1= 6]); + int negx =3D 0, negf =3D 0; + + if (is_s) { + if (env->vfp.fpcr & FPCR_AH) { + negf =3D float_muladd_negate_product; + } else { + negx =3D 0x8000; + } + } =20 for (i =3D 0; i < oprsz; i +=3D sizeof(float32)) { - float16 nn_16 =3D *(float16 *)(vn + H1_2(i + sel)) ^ negn; + float16 nn_16 =3D *(float16 *)(vn + H1_2(i + sel)) ^ negx; float16 mm_16 =3D *(float16 *)(vm + H1_2(i + sel)); float32 nn =3D float16_to_float32_by_bits(nn_16, fz16); float32 mm =3D float16_to_float32_by_bits(mm_16, fz16); float32 aa =3D *(float32 *)(va + H1_4(i)); =20 - *(float32 *)(vd + H1_4(i)) =3D float32_muladd(nn, mm, aa, 0, statu= s); + *(float32 *)(vd + H1_4(i)) =3D float32_muladd(nn, mm, aa, negf, st= atus); } } =20 --=20 2.43.0