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By doing an automated conversion of the whole file we avoid possibly using more than one fpst value in a set_rmode/op/restore_rmode sequence. Patch created with perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A64_F16/g' target/arm/tcg/transl= ate-{a64,sve,sme}.c Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250124162836.2332150-18-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 32 ++++++++--------- target/arm/tcg/translate-sve.c | 66 +++++++++++++++++----------------- 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d9c00713675..2b8b253479a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -726,7 +726,7 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_= q, int rd, int rn, int rm, bool is_fp16, int data, gen_helper_gvec_3_ptr *fn) { - TCGv_ptr fpst =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64); + TCGv_ptr fpst =3D fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), fpst, @@ -768,7 +768,7 @@ static void gen_gvec_op4_fpst(DisasContext *s, bool is_= q, int rd, int rn, int rm, int ra, bool is_fp16, int data, gen_helper_gvec_4_ptr *fn) { - TCGv_ptr fpst =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64); + TCGv_ptr fpst =3D fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64); tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), @@ -5062,7 +5062,7 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e = *a, const FPScalar *f) if (fp_access_check(s)) { TCGv_i32 t0 =3D read_fp_hreg(s, a->rn); TCGv_i32 t1 =3D read_fp_hreg(s, a->rm); - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); write_fp_sreg(s, a->rd, t0); } break; @@ -5270,9 +5270,9 @@ static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a, TCGv_i32 t0 =3D read_fp_hreg(s, a->rn); TCGv_i32 t1 =3D tcg_constant_i32(0); if (swap) { - f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_FPCR_F16)); + f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_A64_F16)); } else { - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); } write_fp_sreg(s, a->rd, t0); } @@ -6230,7 +6230,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rr= x_e *a, const FPScalar *f) TCGv_i32 t1 =3D tcg_temp_new_i32(); =20 read_vec_element_i32(s, t1, a->rm, a->idx, MO_16); - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); write_fp_sreg(s, a->rd, t0); } break; @@ -6288,7 +6288,7 @@ static bool do_fmla_scalar_idx(DisasContext *s, arg_r= rx_e *a, bool neg) gen_vfp_negh(t1, t1); } gen_helper_advsimd_muladdh(t0, t1, t2, t0, - fpstatus_ptr(FPST_FPCR_F16)); + fpstatus_ptr(FPST_A64_F16)); write_fp_sreg(s, a->rd, t0); } break; @@ -6626,7 +6626,7 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_r= r_e *a, const FPScalar *f) =20 read_vec_element_i32(s, t0, a->rn, 0, MO_16); read_vec_element_i32(s, t1, a->rn, 1, MO_16); - f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16)); + f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_A64_F16)); write_fp_sreg(s, a->rd, t0); } break; @@ -6801,7 +6801,7 @@ static bool do_fmadd(DisasContext *s, arg_rrrr_e *a, = bool neg_a, bool neg_n) if (neg_n) { gen_vfp_negh(tn, tn); } - fpst =3D fpstatus_ptr(FPST_FPCR_F16); + fpst =3D fpstatus_ptr(FPST_A64_F16); gen_helper_advsimd_muladdh(ta, tn, tm, ta, fpst); write_fp_sreg(s, a->rd, ta); } @@ -6895,7 +6895,7 @@ static bool do_fp_reduction(DisasContext *s, arg_qrr_= e *a, if (fp_access_check(s)) { MemOp esz =3D a->esz; int elts =3D (a->q ? 16 : 8) >> esz; - TCGv_ptr fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16 : = FPST_A64); + TCGv_ptr fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : F= PST_A64); TCGv_i32 res =3D do_reduction_op(s, a->rn, esz, 0, elts, fpst, fn); write_fp_sreg(s, a->rd, res); } @@ -6939,7 +6939,7 @@ static void handle_fp_compare(DisasContext *s, int si= ze, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 : FPS= T_A64); + TCGv_ptr fpst =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_A64_F16 : FPST= _A64); =20 if (size =3D=3D MO_64) { TCGv_i64 tcg_vn, tcg_vm; @@ -8407,7 +8407,7 @@ static bool do_fp1_scalar(DisasContext *s, arg_rr_e *= a, return check =3D=3D 0; } =20 - fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64); + fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); if (rmode >=3D 0) { tcg_rmode =3D gen_set_rmode(rmode, fpst); } @@ -8598,7 +8598,7 @@ static bool do_cvtf_scalar(DisasContext *s, MemOp esz= , int rd, int shift, TCGv_i32 tcg_shift, tcg_single; TCGv_i64 tcg_double; =20 - tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_= A64); + tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A= 64); tcg_shift =3D tcg_constant_i32(shift); =20 switch (esz) { @@ -8693,7 +8693,7 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out= , MemOp esz, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift, tcg_rmode, tcg_single; =20 - tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_= A64); + tcg_fpstatus =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A= 64); tcg_shift =3D tcg_constant_i32(shift); tcg_rmode =3D gen_set_rmode(rmode, tcg_fpstatus); =20 @@ -9312,7 +9312,7 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e = *a, return check =3D=3D 0; } =20 - fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64); + fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); if (rmode >=3D 0) { tcg_rmode =3D gen_set_rmode(rmode, fpst); } @@ -9372,7 +9372,7 @@ static bool do_gvec_op2_fpst(DisasContext *s, MemOp e= sz, bool is_q, return check =3D=3D 0; } =20 - fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64); + fpst =3D fpstatus_ptr(esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), fpst, is_q ? 16 : 8, vec_full_reg_size(s), diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index d32a67331df..a7dbea5acd0 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -141,7 +141,7 @@ static bool gen_gvec_fpst_arg_zz(DisasContext *s, gen_h= elper_gvec_2_ptr *fn, arg_rr_esz *a, int data) { return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64= ); + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); } =20 /* Invoke an out-of-line helper on 3 Zregs. */ @@ -191,7 +191,7 @@ static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_= helper_gvec_3_ptr *fn, arg_rrr_esz *a, int data) { return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A6= 4); + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64= ); } =20 /* Invoke an out-of-line helper on 4 Zregs. */ @@ -397,7 +397,7 @@ static bool gen_gvec_fpst_arg_zpzz(DisasContext *s, gen= _helper_gvec_4_ptr *fn, arg_rprr_esz *a) { return gen_gvec_fpst_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A= 64); + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A6= 4); } =20 /* Invoke a vector expander on two Zregs and an immediate. */ @@ -3517,7 +3517,7 @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_es= z *a, bool sub) }; return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, (a->index << 1) | sub, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A= 64); + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A6= 4); } =20 TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false) @@ -3533,7 +3533,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = =3D { }; TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz, fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 /* *** SVE Floating Point Fast Reduction Group @@ -3566,7 +3566,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, =20 tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); - status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64= ); + status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 fn(temp, t_zn, t_pg, status, t_desc); =20 @@ -3618,7 +3618,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a, if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr status =3D - fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64); + fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 tcg_gen_gvec_3_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), @@ -3654,7 +3654,7 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] =3D= { }; TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 /* *** SVE Floating Point Accumulating Reduction Group @@ -3687,7 +3687,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) t_pg =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); - t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64= ); + t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); t_desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); =20 fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); @@ -3762,7 +3762,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int= zn, int pg, bool is_fp16, tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn)); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); =20 - status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_A64); + status =3D fpstatus_ptr(is_fp16 ? FPST_A64_F16 : FPST_A64); desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); fn(t_zd, t_zn, t_pg, scalar, status, desc); } @@ -3814,7 +3814,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *= a, } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F= 16 : FPST_A64); + TCGv_ptr status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F1= 6 : FPST_A64); tcg_gen_gvec_4_ptr(pred_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), vec_full_reg_offset(s, a->rm), @@ -3847,7 +3847,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] =3D { }; TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], a->rd, a->rn, a->rm, a->pg, a->rot, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 #define DO_FMLA(NAME, name) \ static gen_helper_gvec_5_ptr * const name##_fns[4] =3D { \ @@ -3856,7 +3856,7 @@ TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd= _fns[a->esz], }; \ TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_zzzzp, name##_fns[a->esz], \ a->rd, a->rn, a->rm, a->ra, a->pg, 0, \ - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 DO_FMLA(FMLA_zpzzz, fmla_zpzzz) DO_FMLA(FMLS_zpzzz, fmls_zpzzz) @@ -3871,14 +3871,14 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = =3D { }; TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->pg, a->rot, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] =3D { NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL }; TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 /* *** SVE Floating Point Unary Operations Predicated Group @@ -3902,17 +3902,17 @@ TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sd, a, 0, FPST_A64) =20 TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16) + gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16) + gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16) + gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16) + gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16) + gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16) TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16) + gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16) =20 TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64) @@ -3939,7 +3939,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] =3D { gen_helper_sve_frint_d }; TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz], - a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_3_ptr * const frintx_fns[] =3D { NULL, @@ -3948,7 +3948,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] =3D= { gen_helper_sve_frintx_d }; TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], - a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64); + a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, ARMFPRounding mode, gen_helper_gvec_3_ptr *fn) @@ -3965,7 +3965,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_es= z *a, } =20 vsz =3D vec_full_reg_size(s); - status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64= ); + status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); tmode =3D gen_set_rmode(mode, status); =20 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), @@ -3993,21 +3993,21 @@ static gen_helper_gvec_3_ptr * const frecpx_fns[] = =3D { gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d, }; TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz], - a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_3_ptr * const fsqrt_fns[] =3D { NULL, gen_helper_sve_fsqrt_h, gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d, }; TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz], - a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16) + gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16) TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16) + gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16) TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16) + gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16) =20 TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ss, a, 0, FPST_A64) @@ -4020,11 +4020,11 @@ TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zp= z, gen_helper_sve_scvt_dd, a, 0, FPST_A64) =20 TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16) + gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16) TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16) + gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16) TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, - gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16) + gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16) =20 TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ss, a, 0, FPST_A64) @@ -7057,7 +7057,7 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] =3D { gen_helper_flogb_s, gen_helper_flogb_d }; TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz], - a, 0, a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_A64) + a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool= sel) { --=20 2.34.1