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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 28/36] target/arm: Use FPST_A32_F16 in A32 decoder
Date: Tue, 28 Jan 2025 20:13:06 +0000
Message-Id: <20250128201314.44038-29-peter.maydell@linaro.org>
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In the A32 decoder, use FPST_A32_F16 rather than FPST_FPCR_F16.
By doing an automated conversion of the whole file we avoid possibly
using more than one fpst value in a set_rmode/op/restore_rmode
sequence.
Patch created with
perl -p -i -e 's/FPST_FPCR_F16(?!_)/FPST_A32_F16/g' target/arm/tcg/transl=
ate-vfp.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-17-peter.maydell@linaro.org
---
target/arm/tcg/translate-vfp.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index c82f41234cd..8d9d1ab877a 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -460,7 +460,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
}
=20
if (sz =3D=3D 1) {
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
} else {
fpst =3D fpstatus_ptr(FPST_A32);
}
@@ -527,7 +527,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
=20
if (sz =3D=3D 1) {
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
} else {
fpst =3D fpstatus_ptr(FPST_A32);
}
@@ -1433,7 +1433,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpS=
PFn *fn,
/*
* Do a half-precision operation. Functionally this is
* the same as do_vfp_3op_sp(), except:
- * - it uses the FPST_FPCR_F16
+ * - it uses the FPST_A32_F16
* - it doesn't need the VFP vector handling (fp16 is a
* v8 feature, and in v8 VFP vectors don't exist)
* - it does the aa32_fp16_arith feature test
@@ -1456,7 +1456,7 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpS=
PFn *fn,
f0 =3D tcg_temp_new_i32();
f1 =3D tcg_temp_new_i32();
fd =3D tcg_temp_new_i32();
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
=20
vfp_load_reg16(f0, vn);
vfp_load_reg16(f1, vm);
@@ -2122,7 +2122,7 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a=
, bool neg_n, bool neg_d)
/* VFNMA, VFNMS */
gen_vfp_negh(vd, vd);
}
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
vfp_store_reg32(vd, a->vd);
return true;
@@ -2424,7 +2424,7 @@ DO_VFP_2OP(VNEG, dp, gen_vfp_negd, aa32_fpdp_v2)
=20
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_FPCR_F16));
+ gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_A32_F16));
}
=20
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
@@ -2706,7 +2706,7 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRIN=
TR_sp *a)
=20
tmp =3D tcg_temp_new_i32();
vfp_load_reg16(tmp, a->vm);
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
gen_helper_rinth(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2779,7 +2779,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRIN=
TZ_sp *a)
=20
tmp =3D tcg_temp_new_i32();
vfp_load_reg16(tmp, a->vm);
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
tcg_rmode =3D gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_restore_rmode(tcg_rmode, fpst);
@@ -2859,7 +2859,7 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRIN=
TX_sp *a)
=20
tmp =3D tcg_temp_new_i32();
vfp_load_reg16(tmp, a->vm);
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
gen_helper_rinth_exact(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2983,7 +2983,7 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VC=
VT_int_sp *a)
=20
vm =3D tcg_temp_new_i32();
vfp_load_reg32(vm, a->vm);
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
if (a->s) {
/* i32 -> f16 */
gen_helper_vfp_sitoh(vm, vm, fpst);
@@ -3105,7 +3105,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC=
VT_fix_sp *a)
vd =3D tcg_temp_new_i32();
vfp_load_reg32(vd, a->vd);
=20
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
shift =3D tcg_constant_i32(frac_bits);
=20
/* Switch on op:U:sx bits */
@@ -3273,7 +3273,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VC=
VT_sp_int *a)
return true;
}
=20
- fpst =3D fpstatus_ptr(FPST_FPCR_F16);
+ fpst =3D fpstatus_ptr(FPST_A32_F16);
vm =3D tcg_temp_new_i32();
vfp_load_reg16(vm, a->vm);
=20
--=20
2.34.1