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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/36] target/arm: Remove now-unused vfp.fp_status and
FPST_FPCR
Date: Tue, 28 Jan 2025 20:13:02 +0000
Message-Id: <20250128201314.44038-25-peter.maydell@linaro.org>
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Now we have moved all the uses of vfp.fp_status and FPST_FPCR
to either the A32 or A64 fields, we can remove these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-13-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 --
target/arm/tcg/translate.h | 6 ------
target/arm/cpu.c | 1 -
target/arm/vfp_helper.c | 8 +-------
4 files changed, 1 insertion(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 337c5383748..7b967bbd1d2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -633,7 +633,6 @@ typedef struct CPUArchState {
=20
/* There are a number of distinct float control structures:
*
- * fp_status: is the "normal" fp status.
* fp_status_a32: is the "normal" fp status for AArch32 insns
* fp_status_a64: is the "normal" fp status for AArch64 insns
* fp_status_fp16: used for half-precision calculations
@@ -660,7 +659,6 @@ typedef struct CPUArchState {
* only thing which needs to read the exception flags being
* an explicit FPSCR read.
*/
- float_status fp_status;
float_status fp_status_a32;
float_status fp_status_a64;
float_status fp_status_f16;
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index c8414d94d5e..fca68b7c4c8 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -670,7 +670,6 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const T=
ranslationBlock *tb)
* Enum for argument to fpstatus_ptr().
*/
typedef enum ARMFPStatusFlavour {
- FPST_FPCR,
FPST_A32,
FPST_A64,
FPST_FPCR_F16,
@@ -686,8 +685,6 @@ typedef enum ARMFPStatusFlavour {
* been set up to point to the requested field in the CPU state struct.
* The options are:
*
- * FPST_FPCR
- * for non-FP16 operations controlled by the FPCR
* FPST_A32
* for AArch32 non-FP16 operations controlled by the FPCR
* FPST_A64
@@ -705,9 +702,6 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour =
flavour)
int offset;
=20
switch (flavour) {
- case FPST_FPCR:
- offset =3D offsetof(CPUARMState, vfp.fp_status);
- break;
case FPST_A32:
offset =3D offsetof(CPUARMState, vfp.fp_status_a32);
break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8bdd535db95..a2b9bd3fb9d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -572,7 +572,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t=
ype)
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
- arm_set_default_fp_behaviours(&env->vfp.fp_status);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
arm_set_default_fp_behaviours(&env->vfp.standard_fp_status);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 034f26e5daa..9fee6265f20 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -61,9 +61,8 @@ static inline uint32_t vfp_exceptbits_from_host(int host_=
bits)
=20
static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
{
- uint32_t i;
+ uint32_t i =3D 0;
=20
- i =3D get_float_exception_flags(&env->vfp.fp_status);
i |=3D get_float_exception_flags(&env->vfp.fp_status_a32);
i |=3D get_float_exception_flags(&env->vfp.fp_status_a64);
i |=3D get_float_exception_flags(&env->vfp.standard_fp_status);
@@ -82,7 +81,6 @@ static void vfp_clear_float_status_exc_flags(CPUARMState =
*env)
* values. The caller should have arranged for env->vfp.fpsr to
* be the architecturally up-to-date exception flag information first.
*/
- set_float_exception_flags(0, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.fp_status_a32);
set_float_exception_flags(0, &env->vfp.fp_status_a64);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
@@ -112,7 +110,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint=
32_t val, uint32_t mask)
i =3D float_round_to_zero;
break;
}
- set_float_rounding_mode(i, &env->vfp.fp_status);
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
set_float_rounding_mode(i, &env->vfp.fp_status_a64);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
@@ -126,8 +123,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint=
32_t val, uint32_t mask)
}
if (changed & FPCR_FZ) {
bool ftz_enabled =3D val & FPCR_FZ;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
@@ -135,7 +130,6 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint=
32_t val, uint32_t mask)
}
if (changed & FPCR_DN) {
bool dnan_enabled =3D val & FPCR_DN;
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
--=20
2.34.1