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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd4fa3efsm182524105e9.2.2025.01.28.12.13.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 12:13:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738095208; x=1738700008; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YfmFIALECF1YnPo5TXCJA57O7vPBexNzDejZbEElEkM=; b=DG6l2ZcmGNKAENqaYaObEcx6o5i2K0alftcMPwE0sRLgXmBozVHyFD3E2+jUPTsZ/8 tvEaF321fIISPus4wUb6+oAtEnH/76mmUziqQFXiIpFnX6ZYIPBXrIFTQaXZ7udOzf70 TgMHATrIwWYWcdeR4J1Ra6s6/U2t5EzuxTWBtSNPByrhnXq8yyE+Ud54joUOrtuBs5dt cVpE6J7ZLl1I2J3JOiGx2T6QnPnMDMaDdPSxuR4bob2ssvTFjN17OtdHAIWau/bsU8lH 7xxC/LHsmitkdToYuQnmuaBy5RiCaW//QfxvkYsFaF54dOo0Ek0MsPHhviqxRahG035P MUqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738095208; x=1738700008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YfmFIALECF1YnPo5TXCJA57O7vPBexNzDejZbEElEkM=; b=TjAm1q7gkH3RraSraRVMkYo/vXqohJnUlzdAtQgX58Nub5FXsoC5dmxxg5p4n37aU8 I5fsy9ELQ5S/H2BvQYxtdT1fbJnjaTTVsCOGRzq2j9Rwlqqnv7D7gh5+zKJjo/c8gz8E IRgjCglAlLGZ2iQHFAIYG92+SuDELTob6zkqzYlj7LPpH7WocwIo3RB5V1OBurpiAc1O 5QE+cc8HWrEyJXtghbUlgq313xFUn3Isoh7/Qu6dtsfMqowPZhhzmbGUdbRCCulDPgzZ C1kBlFjupp73K1pm51Z1oSxNsJvlVaBzXbA8O3E+d0Aw0B/lpQZ6lvhifYWreKtkgLTy pAdg== X-Gm-Message-State: AOJu0YwwWpFGvCnLPwuc4T0/qSm5gVN67fq41XGQaa8G3/OUqBjaM4gK KHvP11GeQ/hNapcZ16uXI37YsSPR7pBCmHVWJA08KjurISsqQivVaPJOCbDHo7mg76WFJgk/B8a c X-Gm-Gg: ASbGncsJB1vzJyaPSKcAHLqEvG7+zNREyfMFHvBM/3Pd3W5eaeZDnZADv7FbEpXlDB6 HpOVTdg2+hq2UzcwPRgfW7Vpltt4xePFvy3Rpf5FavAa0gnntMaPkMex9zwwY/345CAQxOINoCO UF/bTolOW8udZVdAreRBcjF8k7cLYlY2np1n2Wm/BvSrEOO1OF3aoRNTO+V4oSxN4XGfURvz+bR GmcLRac7D2r5cxUeDM7neo+Db80CqMBxxWFAZk7hrP6I21kBXXPLQH8Q7R/iT9avzNmCkeJL/X+ lOv0/saOFBOo3RMeyPPuaNfF94wgubfb X-Google-Smtp-Source: AGHT+IGNl4rUSc0LzoJ/9S0IooZLaCFZoMltveKnerTTsV9DsFdh7wtzi4qq9KaMgdQAISDt70/Y3A== X-Received: by 2002:a05:600c:4e09:b0:436:1c04:aa8e with SMTP id 5b1f17b1804b1-438dc3c8200mr2700365e9.16.1738095207736; Tue, 28 Jan 2025 12:13:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/36] hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers Date: Tue, 28 Jan 2025 20:12:49 +0000 Message-Id: <20250128201314.44038-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250128201314.44038-1-peter.maydell@linaro.org> References: <20250128201314.44038-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1738095459004019000 From: Philippe Mathieu-Daud=C3=A9 Add definitions (DCx_periph) for the DeviceCapability bits, replace direct bitmask checks with the DEV_CAP() macro, which use the extract/deposit API. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Message-id: 20250110160204.74997-6-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index dd342b17d2a..82f935cb329 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -8,6 +8,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "qapi/error.h" #include "hw/core/split-irq.h" #include "hw/sysbus.h" @@ -54,6 +55,26 @@ #define NUM_GPTM 4 #define NUM_I2C 2 =20 +/* + * See Stellaris Data Sheet chapter 5.2.5 "System Control", + * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4). + */ +#define DC1_WDT 3 +#define DC1_HIB 6 +#define DC1_MPU 7 +#define DC1_ADC 16 +#define DC1_PWM 20 +#define DC2_UART(n) (n) +#define DC2_SSI 4 +#define DC2_QEI(n) (8 + n) +#define DC2_I2C(n) (12 + 2 * n) +#define DC2_GPTM(n) (16 + n) +#define DC2_COMP(n) (24 + n) +#define DC4_GPIO(n) (n) +#define DC4_EMAC 28 + +#define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1) + typedef const struct { const char *name; uint32_t did0; @@ -1118,7 +1139,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic,= 28)); =20 - if (board->dc1 & (1 << 16)) { + if (DEV_CAP(1, ADC)) { dev =3D sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), qdev_get_gpio_in(nvic, 15), @@ -1130,7 +1151,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) adc =3D NULL; } for (i =3D 0; i < NUM_GPTM; i++) { - if (board->dc2 & (0x10000 << i)) { + if (DEV_CAP(2, GPTM(i))) { SysBusDevice *sbd; =20 dev =3D qdev_new(TYPE_STELLARIS_GPTM); @@ -1147,7 +1168,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) } } =20 - if (board->dc1 & (1 << 3)) { /* watchdog present */ + if (DEV_CAP(1, WDT)) { dev =3D qdev_new(TYPE_LUMINARY_WATCHDOG); object_property_add_child(soc_container, "wdg", OBJECT(dev)); qdev_connect_clock_in(dev, "WDOGCLK", @@ -1164,7 +1185,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) =20 =20 for (i =3D 0; i < NUM_GPIO; i++) { - if (board->dc4 & (1 << i)) { + if (DEV_CAP(4, GPIO(i))) { gpio_dev[i] =3D sysbus_create_simple("pl061_luminary", gpio_ad= dr[i], qdev_get_gpio_in(nvic, gpio_irq[i= ])); @@ -1175,7 +1196,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) } } =20 - if (board->dc2 & (1 << 12)) { + if (DEV_CAP(2, I2C(0))) { dev =3D sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, qdev_get_gpio_in(nvic, 8)); i2c =3D (I2CBus *)qdev_get_child_bus(dev, "i2c"); @@ -1185,7 +1206,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) } =20 for (i =3D 0; i < NUM_UART; i++) { - if (board->dc2 & (1 << i)) { + if (DEV_CAP(2, UART(i))) { SysBusDevice *sbd; =20 dev =3D qdev_new("pl011_luminary"); @@ -1197,7 +1218,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])= ); } } - if (board->dc2 & (1 << 4)) { + if (DEV_CAP(2, SSI)) { dev =3D sysbus_create_simple("pl022", 0x40008000, qdev_get_gpio_in(nvic, 7)); if (board->peripherals & BP_OLED_SSI) { @@ -1306,7 +1327,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) qemu_irq_raise(gpio_out[GPIO_D][0]); } } - if (board->dc4 & (1 << 28)) { + if (DEV_CAP(4, EMAC)) { DeviceState *enet; =20 enet =3D qdev_new("stellaris_enet"); --=20 2.34.1