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Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 10 +++++----- target/arm/vfp_helper.c | 16 ++++++++-------- 5 files changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 06dbee5725..05a58de045 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -691,7 +691,6 @@ typedef struct CPUArchState { float_status fp_status[FPST_COUNT]; struct { float_status fp_status_a32; - float_status fp_status_a64; }; }; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ceb2dcb3fb..777e5f5dd8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -551,7 +551,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status_a32); - arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 6e336e10c6..dcc48e43db 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1044,7 +1044,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *= vzm, void *vpn, * round-to-odd -- see above. */ fpst_f16 =3D env->vfp.fp_status[FPST_A64_F16]; - fpst_std =3D env->vfp.fp_status_a64; + fpst_std =3D env->vfp.fp_status[FPST_A64]; set_default_nan_mode(true, &fpst_std); set_default_nan_mode(true, &fpst_f16); fpst_odd =3D fpst_std; diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 61f268efad..9ed04b1b0a 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2184,7 +2184,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void = *vm, void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { - do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc, + do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_A64], desc, get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16])); } =20 @@ -2194,7 +2194,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, vo= id *vm, void *va, intptr_t i, oprsz =3D simd_oprsz(desc); uint16_t negn =3D extract32(desc, SIMD_DATA_SHIFT, 1) << 15; intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(floa= t16); - float_status *status =3D &env->vfp.fp_status_a64; + float_status *status =3D &env->vfp.fp_status[FPST_A64]; bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F1= 6]); =20 for (i =3D 0; i < oprsz; i +=3D sizeof(float32)) { @@ -2246,7 +2246,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, v= oid *vm, void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { - do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc, + do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_A64], desc, get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16= ])); } =20 @@ -2257,7 +2257,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, vo= id *vm, void *va, uint16_t negn =3D extract32(desc, SIMD_DATA_SHIFT, 1) << 15; intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(floa= t16); intptr_t idx =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(floa= t16); - float_status *status =3D &env->vfp.fp_status_a64; + float_status *status =3D &env->vfp.fp_status[FPST_A64]; bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F1= 6]); =20 for (i =3D 0; i < oprsz; i +=3D 16) { @@ -2936,7 +2936,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp, = float_status *oddstatusp) */ bool ebf =3D is_a64(env) && env->vfp.fpcr & FPCR_EBF; =20 - *statusp =3D env->vfp.fp_status_a64; + *statusp =3D env->vfp.fp_status[FPST_A64]; set_default_nan_mode(true, statusp); =20 if (ebf) { diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 6a6eb48530..e0d0623097 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -125,7 +125,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) a32_flags |=3D (get_float_exception_flags(&env->vfp.fp_status[FPST_STD= _F16]) & ~float_flag_input_denormal_flushed); =20 - a64_flags |=3D get_float_exception_flags(&env->vfp.fp_status_a64); + a64_flags |=3D get_float_exception_flags(&env->vfp.fp_status[FPST_A64]= ); a64_flags |=3D (get_float_exception_flags(&env->vfp.fp_status[FPST_A64= _F16]) & ~(float_flag_input_denormal_flushed | float_flag_input_denorma= l_used)); /* @@ -154,7 +154,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMStat= e *env) * be the architecturally up-to-date exception flag information first. */ set_float_exception_flags(0, &env->vfp.fp_status_a32); - set_float_exception_flags(0, &env->vfp.fp_status_a64); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); @@ -197,7 +197,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint= 32_t val, uint32_t mask) break; } set_float_rounding_mode(i, &env->vfp.fp_status_a32); - set_float_rounding_mode(i, &env->vfp.fp_status_a64); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); } @@ -215,7 +215,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint= 32_t val, uint32_t mask) if (changed & FPCR_FZ) { bool ftz_enabled =3D val & FPCR_FZ; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32); - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]); /* FIZ is A64 only so FZ always makes A32 code flush inputs to zer= o */ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32); } @@ -226,12 +226,12 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, ui= nt32_t val, uint32_t mask) */ bool fitz_enabled =3D (val & FPCR_FIZ) || (val & (FPCR_FZ | FPCR_AH)) =3D=3D FPCR_FZ; - set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status_a64); + set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_A6= 4]); } if (changed & FPCR_DN) { bool dnan_enabled =3D val & FPCR_DN; set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F1= 6]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F1= 6]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); @@ -242,10 +242,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, ui= nt32_t val, uint32_t mask) =20 if (ah_enabled) { /* Change behaviours for A64 FP operations */ - arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); } else { - arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16= ]); } } --=20 2.43.0