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Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/cpu.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 8 ++++---- target/arm/vfp_helper.c | 16 ++++++++-------- 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e3d952588..9e39c8d0d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -693,7 +693,6 @@ typedef struct CPUArchState { float_status fp_status_a32; float_status fp_status_a64; float_status fp_status_f16_a32; - float_status fp_status_f16_a64; }; }; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01a0428c6e..4fc1d00d60 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -554,7 +554,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a32); - arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 727c085f37..6e336e10c6 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1043,7 +1043,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *= vzm, void *vpn, * produces default NaNs. We also need a second copy of fp_status with * round-to-odd -- see above. */ - fpst_f16 =3D env->vfp.fp_status_f16_a64; + fpst_f16 =3D env->vfp.fp_status[FPST_A64_F16]; fpst_std =3D env->vfp.fp_status_a64; set_default_nan_mode(true, &fpst_std); set_default_nan_mode(true, &fpst_f16); diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 60839ae560..927dece4c1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2185,7 +2185,7 @@ void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void = *vm, CPUARMState *env, uint32_t desc) { do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc, - get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64)); + get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16])); } =20 void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va, @@ -2195,7 +2195,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, vo= id *vm, void *va, uint16_t negn =3D extract32(desc, SIMD_DATA_SHIFT, 1) << 15; intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(floa= t16); float_status *status =3D &env->vfp.fp_status_a64; - bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64); + bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F1= 6]); =20 for (i =3D 0; i < oprsz; i +=3D sizeof(float32)) { float16 nn_16 =3D *(float16 *)(vn + H1_2(i + sel)) ^ negn; @@ -2247,7 +2247,7 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, v= oid *vm, CPUARMState *env, uint32_t desc) { do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc, - get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64)); + get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16= ])); } =20 void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va, @@ -2258,7 +2258,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, vo= id *vm, void *va, intptr_t sel =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(floa= t16); intptr_t idx =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(floa= t16); float_status *status =3D &env->vfp.fp_status_a64; - bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64); + bool fz16 =3D get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F1= 6]); =20 for (i =3D 0; i < oprsz; i +=3D 16) { float16 mm_16 =3D *(float16 *)(vm + i + idx); diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 78be434caf..bcb05d7ff9 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -126,7 +126,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) & ~float_flag_input_denormal_flushed); =20 a64_flags |=3D get_float_exception_flags(&env->vfp.fp_status_a64); - a64_flags |=3D (get_float_exception_flags(&env->vfp.fp_status_f16_a64) + a64_flags |=3D (get_float_exception_flags(&env->vfp.fp_status[FPST_A64= _F16]) & ~(float_flag_input_denormal_flushed | float_flag_input_denorma= l_used)); /* * We do not merge in flags from FPST_AH or FPST_AH_F16, because @@ -156,7 +156,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMStat= e *env) set_float_exception_flags(0, &env->vfp.fp_status_a32); set_float_exception_flags(0, &env->vfp.fp_status_a64); set_float_exception_flags(0, &env->vfp.fp_status_f16_a32); - set_float_exception_flags(0, &env->vfp.fp_status_f16_a64); + set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH]); @@ -199,16 +199,16 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, ui= nt32_t val, uint32_t mask) set_float_rounding_mode(i, &env->vfp.fp_status_a32); set_float_rounding_mode(i, &env->vfp.fp_status_a64); set_float_rounding_mode(i, &env->vfp.fp_status_f16_a32); - set_float_rounding_mode(i, &env->vfp.fp_status_f16_a64); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); } if (changed & FPCR_FZ16) { bool ftz_enabled =3D val & FPCR_FZ16; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a32); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16_a64); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64= _F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD= _F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_= F16]); } @@ -233,7 +233,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint= 32_t val, uint32_t mask) set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a32); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16_a64); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F1= 6]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16= ]); } @@ -243,10 +243,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, ui= nt32_t val, uint32_t mask) if (ah_enabled) { /* Change behaviours for A64 FP operations */ arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64); - arm_set_ah_fp_behaviours(&env->vfp.fp_status_f16_a64); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); } else { arm_set_default_fp_behaviours(&env->vfp.fp_status_a64); - arm_set_default_fp_behaviours(&env->vfp.fp_status_f16_a64); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16= ]); } } /* --=20 2.43.0