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To: qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org, Roman Artemev <roman.artemev@syntacore.com>,
Richard Henderson <richard.henderson@linaro.org>,
Denis Tomashev <denis.tomashev@syntacore.com>,
Michael Tokarev <mjt@tls.msk.ru>
Subject: [Stable-9.1.3 27/58] tcg/riscv: Fix StoreStore barrier generation
Date: Mon, 27 Jan 2025 23:25:13 +0300
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On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`
Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit b438362a142527b97b638b7f0f35ebe11911a8d5)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index d334857226..73bbb4cd67 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1149,7 +1149,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
insn |=3D 0x02100000;
}
if (a0 & TCG_MO_ST_ST) {
- insn |=3D 0x02200000;
+ insn |=3D 0x01100000;
}
tcg_out32(s, insn);
}
--=20
2.39.5