From nobody Sat Apr 5 15:56:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1738052286903564.183538337629; Tue, 28 Jan 2025 00:18:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tcgaO-0001f6-Bg; Tue, 28 Jan 2025 03:04:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcgYW-0006Kw-6H; Tue, 28 Jan 2025 03:02:45 -0500 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tcgYS-0002B9-CR; Tue, 28 Jan 2025 03:02:41 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id CBD75E1B5B; Tue, 28 Jan 2025 10:57:08 +0300 (MSK) Received: from localhost.tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with ESMTP id 47A4A1A630E; Tue, 28 Jan 2025 10:57:34 +0300 (MSK) Received: by localhost.tls.msk.ru (Postfix, from userid 1000) id 09ACB520AD; Tue, 28 Jan 2025 10:57:34 +0300 (MSK) To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Glenn Miles , Nicholas Piggin , Michael Tokarev Subject: [Stable-9.1.3 20/58] target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket Date: Mon, 27 Jan 2025 23:25:06 +0300 Message-Id: <20250127202547.3723716-20-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Tokarev Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_06_12=1.543, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1738052288483019000 Content-Type: text/plain; charset="utf-8" The THREAD_SIBLING_FOREACH macro wasn't excluding threads from other chips. Add chip_index field to the thread state and add a check for the new field in the macro. Fixes: b769d4c8f4c6 ("target/ppc: Add initial flags and helpers for SMT sup= port") Signed-off-by: Glenn Miles [npiggin: set chip_index for spapr too] Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin (cherry picked from commit 2fc0a78a57731fda50d5b01e16fd68681900f709) Signed-off-by: Michael Tokarev diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index a30693990b..9441d14bfc 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -317,6 +317,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, pir_spr->default_value =3D pir; tir_spr->default_value =3D tir; =20 + env->chip_index =3D pc->chip->chip_id; + if (pc->big_core) { /* 2 "small cores" get the same core index for SMT operations */ env->core_index =3D core_hwid >> 1; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 56090abcd1..2ada5c9225 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -317,6 +317,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, = int i, Error **errp) return NULL; } =20 + env->chip_index =3D sc->node_id; env->core_index =3D cc->core_id; =20 cpu->node_id =3D sc->node_id; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f7a2da2bbe..4469c15708 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1251,6 +1251,7 @@ struct CPUArchState { /* For SMT processors */ bool has_smt_siblings; int core_index; + int chip_index; =20 #if !defined(CONFIG_USER_ONLY) /* MMU context, only relevant for full system emulation */ @@ -1409,8 +1410,10 @@ struct CPUArchState { =20 #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ CPU_FOREACH(cs_sibling) \ - if (POWERPC_CPU(cs)->env.core_index =3D=3D \ - POWERPC_CPU(cs_sibling)->env.core_index) + if ((POWERPC_CPU(cs)->env.chip_index =3D=3D \ + POWERPC_CPU(cs_sibling)->env.chip_index) && \ + (POWERPC_CPU(cs)->env.core_index =3D=3D \ + POWERPC_CPU(cs_sibling)->env.core_index)) =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ do { \ --=20 2.39.5