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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438bd48574csm130454235e9.9.2025.01.27.03.55.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Jan 2025 03:55:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737978902; x=1738583702; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B4IS3z5t6aeYLZ7NAuHNel+nPJsLHRUkUZSl5ZYMkwc=; b=knJHu9SyuiZHxjrTdCFTk5xLIAODPj6854jIhzC/TQhm2RzIu/EE0qY+fnHPRekzuw BypN6mGXmoxhwK3Oyf4HDwyYWoSUPGNIYe9PPLOWuqGa7Un2ez2+vGTHUwlE1Hj/Cd61 80YSTPOEL1cqRhSbTtE9XTgjIIbVAeWJdU4oRGyFMnUK7PxqGiur5FwxhQY+d4xqcv75 bnZe6ZcMeiEfkBg0JqgByxje+sixQ7n7zQbgo+vcR9vMgM0p8Hi4Ado4YlUiUE7iYTZz zroleyWXpcKe8NJdl8O7/8IO6zugb7MUulvdM/vEEjNeHsjOgUCddqj7fvQ5vmBSwgSF p6Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737978902; x=1738583702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B4IS3z5t6aeYLZ7NAuHNel+nPJsLHRUkUZSl5ZYMkwc=; b=b4mrIabQR2Xsc4BWvb7zVevlYFY2+X50yWOTtrXS8oYY+pDZ9x03v1l8nVBtRmzex9 fDRYTt+beBJJ1oaxxrTk/9fTI4DLmn/IjzYyQlDZVHByCH1+X1Lxn57AKfuKSV7VoEEz Uig9avQoU8lt43EbA9olRuoP+7t7vXW3AmjueNFFLhcos7NNU52uiQqXyA0AnIyOtJBy 4aRwRxPr1vDBrpPFKN/+vw2He1cytBMmTYBOEKHeSh2yuktamzaKNR+2l97WNMlWluhc VwegXOhyZB/Tjq+LfFctRhumhA+e1XuVF4qkgD9QwBpZ0BgmxfCa31YXlnW4aSAhYJAE V33A== X-Gm-Message-State: AOJu0Yyc2vSDKHx/7WreUnTPAS1bIM8SnWhXaE9nO4DU4WuGxce5AQhx SBknutGjkbcbmv4N8ExsHsPCdQeZv+DaKWnssUIRJJgfL7iBzA+JwHbXgIw7/biWbFdCM2zM/9J GmKk= X-Gm-Gg: ASbGnctuzI2Vo5ZdKv413xbMSM9Mabiogli5b7PLYprRF1gSVCRgjIk3OyomJDOMj5X nvahiU6ZCAs8bGXDEScczCDsMFNrqI3bCXUUE7ZawDB0ICuVnIFoHd+16M5mP/+5CJ/c4jvZBsu L4D2l1IA1olSo1MVSCo9ns4uIxSqPp16RwhST1bHT/B9PQApmWXwSw9m/Apbm+3e/UZMoWsaJMk wdjkkBakXxXhyFTKsqEI+PUz8cj2eTtuISuyiZNLVpsZkSe7KmM/xVxKqzIpWFm1FlEVFaFMuHz TrbgUs4n66bqP5Fbmwh34ftg6CePZNO541xFGvcMZMQlv1grllGbhAg= X-Google-Smtp-Source: AGHT+IHET3rqSbR9s6dSwCNjBB9cODBqyhqFPWhEqy/MaP3DAHoJvFDTTKe8eo5it+0lahivn9T4jQ== X-Received: by 2002:a05:600c:3546:b0:434:fc5d:179c with SMTP id 5b1f17b1804b1-438b885f8ebmr162465155e9.13.1737978901751; Mon, 27 Jan 2025 03:55:01 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , qemu-riscv@nongnu.org, Peter Maydell , Richard Henderson , Thomas Huth , qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/10] target/riscv: Set disassemble_info::endian value in disas_set_info() Date: Mon, 27 Jan 2025 12:54:23 +0100 Message-ID: <20250127115426.51355-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250127115426.51355-1-philmd@linaro.org> References: <20250127115426.51355-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737978984076019000 Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- target/riscv/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2c..b39a701d751 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1156,6 +1156,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, di= sassemble_info *info) CPURISCVState *env =3D &cpu->env; info->target_info =3D &cpu->cfg; =20 + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + info->endian =3D BFD_ENDIAN_LITTLE; + switch (env->xl) { case MXL_RV32: info->print_insn =3D print_insn_riscv32; --=20 2.47.1