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From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
Paolo Bonzini <pbonzini@redhat.com>, qemu-riscv@nongnu.org,
Peter Maydell <peter.maydell@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
Thomas Huth <thuth@redhat.com>, qemu-ppc@nongnu.org,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH 01/10] target: Set disassemble_info::endian value for
little-endian targets
Date: Mon, 27 Jan 2025 12:54:17 +0100
Message-ID: <20250127115426.51355-2-philmd@linaro.org>
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Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for little-endian targets.
Note, there was no disas_set_info() handler registered
for the TriCore target, so we implement one.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
target/alpha/cpu.c | 1 +
target/avr/cpu.c | 1 +
target/hexagon/cpu.c | 1 +
target/i386/cpu.c | 1 +
target/loongarch/cpu.c | 1 +
target/rx/cpu.c | 1 +
target/tricore/cpu.c | 6 ++++++
7 files changed, 12 insertions(+)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index da21f99a6ac..acf81fda371 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -85,6 +85,7 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
=20
static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian =3D BFD_ENDIAN_LITTLE;
info->mach =3D bfd_mach_alpha_ev6;
info->print_insn =3D print_insn_alpha;
}
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5a0e21465e5..2871d30540a 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -102,6 +102,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType t=
ype)
=20
static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian =3D BFD_ENDIAN_LITTLE;
info->mach =3D bfd_arch_avr;
info->print_insn =3D avr_print_insn;
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 238e63bcea4..a9beb9a1757 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -293,6 +293,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy=
pe type)
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
info->print_insn =3D print_insn_hexagon;
+ info->endian =3D BFD_ENDIAN_LITTLE;
}
=20
static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1b9c11022c4..eecb6f54d9e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8343,6 +8343,7 @@ static void x86_disas_set_info(CPUState *cs, disassem=
ble_info *info)
X86CPU *cpu =3D X86_CPU(cs);
CPUX86State *env =3D &cpu->env;
=20
+ info->endian =3D BFD_ENDIAN_LITTLE;
info->mach =3D (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
: env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
: bfd_mach_i386_i8086);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 227870e2856..cb9b9f909f3 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -617,6 +617,7 @@ static void loongarch_cpu_reset_hold(Object *obj, Reset=
Type type)
=20
static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *in=
fo)
{
+ info->endian =3D BFD_ENDIAN_LITTLE;
info->print_insn =3D print_insn_loongarch;
}
=20
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index d237d007023..f283315474c 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -160,6 +160,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int re=
quest)
=20
static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
+ info->endian =3D BFD_ENDIAN_LITTLE;
info->mach =3D bfd_mach_rx;
info->print_insn =3D print_insn_rx;
}
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index eb794674c8d..49c18a0cd92 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -35,6 +35,11 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs)
return "tricore";
}
=20
+static void tricore_cpu_disas_set_info(CPUState *cpu, disassemble_info *in=
fo)
+{
+ info->endian =3D BFD_ENDIAN_LITTLE;
+}
+
static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
{
cpu_env(cs)->PC =3D value & ~(target_ulong)1;
@@ -201,6 +206,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void=
*data)
cc->gdb_num_core_regs =3D 44;
cc->gdb_arch_name =3D tricore_gdb_arch_name;
=20
+ cc->disas_set_info =3D tricore_cpu_disas_set_info;
cc->dump_state =3D tricore_cpu_dump_state;
cc->set_pc =3D tricore_cpu_set_pc;
cc->get_pc =3D tricore_cpu_get_pc;
--=20
2.47.1