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From: Anton Blanchard <antonb@tenstorrent.com>
To: qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Cc: Anton Blanchard <antonb@tenstorrent.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [PATCH 04/12] target/riscv: handle vadd.vv form mask and source
overlap
Date: Sun, 26 Jan 2025 07:20:48 +0000
Message-Id: <20250126072056.4004912-5-antonb@tenstorrent.com>
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Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr=
ans/trans_rvv.c.inc
index bc2780497e..f5ba1c4280 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -403,6 +403,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int =
vs, int vm)
static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int =
vm)
{
return vext_check_ss(s, vd, vs2, vm) &&
+ require_vm(vm, vs1) &&
require_align(vs1, s->lmul);
}
=20
--=20
2.34.1