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d="scan'208";a="107897778" From: Zhao Liu To: Paolo Bonzini , Manos Pitsidianakis , Junjie Mao , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, qemu-rust@nongnu.org, Zhao Liu Subject: [PATCH 09/10] rust/timer/hpet: add qom and qdev APIs support Date: Sat, 25 Jan 2025 20:51:36 +0800 Message-Id: <20250125125137.1223277-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250125125137.1223277-1-zhao1.liu@intel.com> References: <20250125125137.1223277-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.18; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -73 X-Spam_score: -7.4 X-Spam_bar: ------- X-Spam_report: (-7.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1737808510154019100 Content-Type: text/plain; charset="utf-8" Implement QOM & QAPI support for HPET device. Signed-off-by: Zhao Liu --- Changes since RFC: * Merge qdev.rs to hpet.rs. * Apply memory and Resettable bindings. * Consolidate inmutable &self and QOM casting. * Prefer timer iterator over loop. * Move init_mmio() and init_irq() to post_init(). --- rust/hw/timer/hpet/src/fw_cfg.rs | 2 - rust/hw/timer/hpet/src/hpet.rs | 283 ++++++++++++++++++++++++++++++- rust/hw/timer/hpet/src/lib.rs | 4 + 3 files changed, 279 insertions(+), 10 deletions(-) diff --git a/rust/hw/timer/hpet/src/fw_cfg.rs b/rust/hw/timer/hpet/src/fw_c= fg.rs index 2f72bf854a66..5223629576a1 100644 --- a/rust/hw/timer/hpet/src/fw_cfg.rs +++ b/rust/hw/timer/hpet/src/fw_cfg.rs @@ -2,8 +2,6 @@ // Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 -#![allow(dead_code)] - use qemu_api::{cell::bql_locked, impl_zeroable, zeroable::Zeroable}; =20 // Each HPETState represents a Event Timer Block. The v1 spec supports diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs index 0884a2ac73c4..7a717dbcfdd0 100644 --- a/rust/hw/timer/hpet/src/hpet.rs +++ b/rust/hw/timer/hpet/src/hpet.rs @@ -2,21 +2,30 @@ // Author(s): Zhao Liu // SPDX-License-Identifier: GPL-2.0-or-later =20 -#![allow(dead_code)] - -use core::ptr::{null_mut, NonNull}; +use core::ptr::{addr_of_mut, null_mut, NonNull}; +use std::{ffi::CStr, slice::from_ref}; =20 use qemu_api::{ - bindings::{address_space_memory, address_space_stl_le, MemoryRegion, S= CALE_NS}, + bindings::{ + address_space_memory, address_space_stl_le, qdev_prop_bit, qdev_pr= op_bool, + qdev_prop_uint32, qdev_prop_uint8, SCALE_NS, + }, + c_str, cell::{BqlCell, BqlRefCell}, irq::InterruptSource, - memory::MEMTXATTRS_UNSPECIFIED, + memory::{ + hwaddr, MemoryRegion, MemoryRegionOps, MemoryRegionOpsBuilder, MEM= TXATTRS_UNSPECIFIED, + }, prelude::*, - qom::ParentField, - sysbus::SysBusDevice, + qdev::{DeviceImpl, DeviceMethods, DeviceState, Property, ResetType, Re= settablePhasesImpl}, + qom::{ClassInitImpl, ObjectImpl, ObjectType, ParentField}, + qom_isa, + sysbus::{SysBusDevice, SysBusDeviceClass}, timer::{QEMUTimer, CLOCK_VIRTUAL}, }; =20 +use crate::fw_cfg::HPETFwConfig; + // Register space for each timer block. (HPET_BASE isn't defined here.) const HPET_REG_SPACE_LEN: u64 =3D 0x400; // 1024 bytes =20 @@ -451,13 +460,43 @@ fn callback(&mut self) { } self.update_irq(true); } + + fn read(&mut self, addr: hwaddr, _size: u32) -> u64 { + let shift: u64 =3D (addr & 4) * 8; + + match addr { + HPET_TN_CFG_REG =3D> self.config >> shift, // including interr= upt capabilities + HPET_TN_CMP_REG =3D> self.cmp >> shift, // comparator regis= ter + HPET_TN_FSB_ROUTE_REG =3D> self.fsb >> shift, + _ =3D> { + // TODO: Add trace point - trace_hpet_ram_read_invalid() + // Reserved. + 0 + } + } + } + + fn write(&mut self, addr: hwaddr, value: u64, size: u32) { + let shift =3D ((addr & 4) * 8) as u32; + let len =3D std::cmp::min(size * 8, 64 - shift); + + match addr { + HPET_TN_CFG_REG =3D> self.set_tn_cfg_reg(shift, len, value), + HPET_TN_CMP_REG =3D> self.set_tn_cmp_reg(shift, len, value), + HPET_TN_FSB_ROUTE_REG =3D> self.set_tn_fsb_route_reg(shift, le= n, value), + _ =3D> { + // TODO: Add trace point - trace_hpet_ram_write_invalid() + // Reserved. + } + } + } } =20 /// HPET Event Timer Block Abstraction /// Note: Wrap all items that may be changed in the callback called by C /// into the BqlCell/BqlRefCell. #[repr(C)] -#[derive(qemu_api_macros::offsets)] +#[derive(qemu_api_macros::Object, qemu_api_macros::offsets)] pub struct HPETState { parent_obj: ParentField, iomem: MemoryRegion, @@ -630,4 +669,232 @@ fn set_counter_reg(&self, shift: u32, len: u32, val: = u64) { self.counter .set(self.counter.get().deposit(shift, len, val)); } + + unsafe fn init(&mut self) { + static HPET_RAM_OPS: MemoryRegionOps =3D + MemoryRegionOpsBuilder::::new() + .read(&HPETState::read) + .write(&HPETState::write) + .native_endian() + .valid_sizes(4, 8) + .impl_sizes(4, 8) + .build(); + + // SAFETY: + // self and self.iomem are guaranteed to be valid at this point si= nce callers + // must make sure the `self` reference is valid. + MemoryRegion::init_io( + unsafe { &mut *addr_of_mut!(self.iomem) }, + addr_of_mut!(*self), + &HPET_RAM_OPS, + "hpet", + HPET_REG_SPACE_LEN, + ); + } + + fn post_init(&self) { + self.init_mmio(&self.iomem); + for irq in self.irqs.iter() { + self.init_irq(irq); + } + } + + fn realize(&self) { + if self.int_route_cap =3D=3D 0 { + // TODO: Add error binding: warn_report() + println!("Hpet's hpet-intcap property not initialized"); + } + + self.hpet_id.set(HPETFwConfig::assign_hpet_id()); + + if self.num_timers.get() < HPET_MIN_TIMERS { + self.num_timers.set(HPET_MIN_TIMERS); + } else if self.num_timers.get() > HPET_MAX_TIMERS { + self.num_timers.set(HPET_MAX_TIMERS); + } + + self.init_timer(); + // 64-bit General Capabilities and ID Register; LegacyReplacementR= oute. + self.capability.set( + HPET_CAP_REV_ID_VALUE << HPET_CAP_REV_ID_SHIFT | + 1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT | + 1 << HPET_CAP_LEG_RT_CAP_SHIFT | + HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT | + ((self.num_timers.get() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT= | // indicate the last timer + (HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT= , // 10 ns + ); + + self.init_gpio_in(2, HPETState::handle_legacy_irq); + self.init_gpio_out(from_ref(&self.pit_enabled)); + } + + fn reset_hold(&self, _type: ResetType) { + let sbd =3D self.upcast::(); + + for timer in self.timers.iter().take(self.num_timers.get()) { + timer.borrow_mut().reset(); + } + + self.counter.set(0); + self.config.set(0); + self.pit_enabled.set(true); + self.hpet_offset.set(0); + + HPETFwConfig::update_hpet_cfg( + self.hpet_id.get(), + Some(self.capability.get() as u32), + Some((*sbd).mmio[0].addr), + ); + + // to document that the RTC lowers its output on reset as well + self.rtc_irq_level.set(0); + } + + fn timer_and_addr(&self, addr: hwaddr) -> Option<(&BqlRefCell, hwaddr)> { + let timer_id: usize =3D ((addr - 0x100) / 0x20) as usize; + + // TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(ti= mer_id) + if timer_id > self.num_timers.get() { + // TODO: Add trace point - trace_hpet_timer_id_out_of_range(t= imer_id) + None + } else { + Some((&self.timers[timer_id], addr & 0x18)) + } + } + + fn read(&self, addr: hwaddr, size: u32) -> u64 { + let shift: u64 =3D (addr & 4) * 8; + + // address range of all TN regs + // TODO: Add trace point - trace_hpet_ram_read(addr) + if (0x100..=3D0x3ff).contains(&addr) { + match self.timer_and_addr(addr) { + None =3D> 0, // Reserved, + Some((timer, addr)) =3D> timer.borrow_mut().read(addr, siz= e), + } + } else { + match addr & !4 { + HPET_CAP_REG =3D> self.capability.get() >> shift, /* inclu= ding HPET_PERIOD 0x004 */ + // (CNT_CLK_PERIOD field) + HPET_CFG_REG =3D> self.config.get() >> shift, + HPET_COUNTER_REG =3D> { + let cur_tick: u64 =3D if self.is_hpet_enabled() { + self.get_ticks() + } else { + self.counter.get() + }; + + // TODO: Add trace point - trace_hpet_ram_read_reading= _counter(addr & 4, + // cur_tick) + cur_tick >> shift + } + HPET_INT_STATUS_REG =3D> self.int_status.get() >> shift, + _ =3D> { + // TODO: Add trace point- trace_hpet_ram_read_invalid() + // Reserved. + 0 + } + } + } + } + + fn write(&self, addr: hwaddr, value: u64, size: u32) { + let shift =3D ((addr & 4) * 8) as u32; + let len =3D std::cmp::min(size * 8, 64 - shift); + + // TODO: Add trace point - trace_hpet_ram_write(addr, value) + if (0x100..=3D0x3ff).contains(&addr) { + match self.timer_and_addr(addr) { + None =3D> return, // Reserved. + Some((timer, addr)) =3D> timer.borrow_mut().write(addr, va= lue, size), + } + } else { + match addr & !0x4 { + HPET_CAP_REG =3D> {} // General Capabilities and ID Regist= er: Read Only + HPET_CFG_REG =3D> self.set_cfg_reg(shift, len, value), + HPET_INT_STATUS_REG =3D> self.set_int_status_reg(shift, le= n, value), + HPET_COUNTER_REG =3D> self.set_counter_reg(shift, len, val= ue), + _ =3D> { + // TODO: Add trace point - trace_hpet_ram_write_invali= d() + // Reserved. + } + } + } + } +} + +qom_isa!(HPETState: SysBusDevice, DeviceState, Object); + +// TODO: add OBJECT_DECLARE_SIMPLE_TYPE. +#[repr(C)] +pub struct HPETClass { + parent_class: ::Class, +} + +unsafe impl ObjectType for HPETState { + type Class =3D HPETClass; + const TYPE_NAME: &'static CStr =3D crate::TYPE_HPET; +} + +impl ClassInitImpl for HPETState { + fn class_init(klass: &mut HPETClass) { + >::class_init(&mut klass.= parent_class); + } +} + +impl ObjectImpl for HPETState { + type ParentType =3D SysBusDevice; + + const INSTANCE_INIT: Option =3D Some(Self::init); + const INSTANCE_POST_INIT: Option =3D Some(Self::post_init); +} + +// TODO: Make these properties user-configurable! +qemu_api::declare_properties! { + HPET_PROPERTIES, + qemu_api::define_property!( + c_str!("timers"), + HPETState, + num_timers, + unsafe { &qdev_prop_uint8 }, + u8, + default =3D HPET_MIN_TIMERS + ), + qemu_api::define_property!( + c_str!("msi"), + HPETState, + flags, + unsafe { &qdev_prop_bit }, + u32, + bit =3D HPET_FLAG_MSI_SUPPORT_SHIFT as u8, + default =3D false, + ), + qemu_api::define_property!( + c_str!("hpet-intcap"), + HPETState, + int_route_cap, + unsafe { &qdev_prop_uint32 }, + u32, + default =3D 0 + ), + qemu_api::define_property!( + c_str!("hpet-offset-saved"), + HPETState, + hpet_offset_saved, + unsafe { &qdev_prop_bool }, + bool, + default =3D true + ), +} + +impl DeviceImpl for HPETState { + fn properties() -> &'static [Property] { + &HPET_PROPERTIES + } + + const REALIZE: Option =3D Some(Self::realize); +} + +impl ResettablePhasesImpl for HPETState { + const HOLD: Option =3D Some(Self::reset_hold); } diff --git a/rust/hw/timer/hpet/src/lib.rs b/rust/hw/timer/hpet/src/lib.rs index 027f7f83349a..25251112a86d 100644 --- a/rust/hw/timer/hpet/src/lib.rs +++ b/rust/hw/timer/hpet/src/lib.rs @@ -10,5 +10,9 @@ =20 #![deny(unsafe_op_in_unsafe_fn)] =20 +use qemu_api::c_str; + pub mod fw_cfg; pub mod hpet; + +pub const TYPE_HPET: &::std::ffi::CStr =3D c_str!("hpet"); --=20 2.34.1