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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH 60/76] target/arm: Handle FPCR.AH in FMLSL
Date: Fri, 24 Jan 2025 16:28:20 +0000
Message-Id: <20250124162836.2332150-61-peter.maydell@linaro.org>
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Honour the FPCR.AH "don't negate the sign of a NaN" semantics in
FMLSL. We pass in the value of FPCR.AH in the SIMD data field, and
use this to determine whether we should suppress the negation for
NaN inputs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 4 ++--
target/arm/tcg/vec_helper.c | 28 ++++++++++++++++++++++++----
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0827dff16b2..e22c2a148ab 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5968,7 +5968,7 @@ TRANS(FMINNMP_v, do_fp3_vector, a, 0, f_vector_fminnm=
p)
static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)
{
if (fp_access_check(s)) {
- int data =3D (is_2 << 1) | is_s;
+ int data =3D (s->fpcr_ah << 2) | (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm), tcg_env,
@@ -6738,7 +6738,7 @@ TRANS(FMLS_vi, do_fmla_vector_idx, a, true)
static bool do_fmlal_idx(DisasContext *s, arg_qrrx_e *a, bool is_s, bool i=
s_2)
{
if (fp_access_check(s)) {
- int data =3D (a->idx << 2) | (is_2 << 1) | is_s;
+ int data =3D (s->fpcr_ah << 5) | (a->idx << 2) | (is_2 << 1) | is_=
s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm), tcg_env,
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 382b5da4a9c..aa42c50f9fe 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2083,6 +2083,26 @@ static uint64_t load4_f16(uint64_t *ptr, int is_q, i=
nt is_2)
return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
}
=20
+static uint64_t neg4_f16(uint64_t v, bool fpcr_ah)
+{
+ /*
+ * Negate all inputs for FMLSL at once. This is slightly complicated
+ * by the need to avoid flipping the sign of a NaN when FPCR.AH =3D=3D=
1
+ */
+ uint64_t mask =3D 0x8000800080008000ull;
+ if (fpcr_ah) {
+ uint64_t tmp =3D v, signbit =3D 0x8000;
+ for (int i =3D 0; i < 4; i++) {
+ if (float16_is_any_nan(extract64(tmp, 0, 16))) {
+ mask ^=3D signbit;
+ }
+ tmp >>=3D 16;
+ signbit <<=3D 16;
+ }
+ }
+ return v ^ mask;
+}
+
/*
* Note that FMLAL requires oprsz =3D=3D 8 or oprsz =3D=3D 16,
* as there is not yet SVE versions that might use blocking.
@@ -2094,6 +2114,7 @@ static void do_fmlal(float32 *d, void *vn, void *vm, =
float_status *fpst,
intptr_t i, oprsz =3D simd_oprsz(desc);
int is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1);
int is_2 =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 2, 1);
int is_q =3D oprsz =3D=3D 16;
uint64_t n_4, m_4;
=20
@@ -2101,9 +2122,8 @@ static void do_fmlal(float32 *d, void *vn, void *vm, =
float_status *fpst,
n_4 =3D load4_f16(vn, is_q, is_2);
m_4 =3D load4_f16(vm, is_q, is_2);
=20
- /* Negate all inputs for FMLSL at once. */
if (is_s) {
- n_4 ^=3D 0x8000800080008000ull;
+ n_4 =3D neg4_f16(n_4, fpcr_ah);
}
=20
for (i =3D 0; i < oprsz / 4; i++) {
@@ -2155,6 +2175,7 @@ static void do_fmlal_idx(float32 *d, void *vn, void *=
vm, float_status *fpst,
int is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1);
int is_2 =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1);
int index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3);
+ bool fpcr_ah =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1);
int is_q =3D oprsz =3D=3D 16;
uint64_t n_4;
float32 m_1;
@@ -2162,9 +2183,8 @@ static void do_fmlal_idx(float32 *d, void *vn, void *=
vm, float_status *fpst,
/* Pre-load all of the f16 data, avoiding overlap issues. */
n_4 =3D load4_f16(vn, is_q, is_2);
=20
- /* Negate all inputs for FMLSL at once. */
if (is_s) {
- n_4 ^=3D 0x8000800080008000ull;
+ n_4 =3D neg4_f16(n_4, fpcr_ah);
}
=20
m_1 =3D float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
--=20
2.34.1