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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH 40/76] target/arm: Handle FPCR.NEP for 1-input scalar
operations
Date: Fri, 24 Jan 2025 16:28:00 +0000
Message-Id: <20250124162836.2332150-41-peter.maydell@linaro.org>
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Handle FPCR.NEP for the 1-input scalar operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 944bdf8cafe..64994d3212f 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8520,17 +8520,17 @@ static bool do_fp1_scalar_with_fpsttype(DisasContex=
t *s, arg_rr_e *a,
case MO_64:
t64 =3D read_fp_dreg(s, a->rn);
f->gen_d(t64, t64, fpst);
- write_fp_dreg(s, a->rd, t64);
+ write_fp_dreg_merging(s, a->rd, a->rd, t64);
break;
case MO_32:
t32 =3D read_fp_sreg(s, a->rn);
f->gen_s(t32, t32, fpst);
- write_fp_sreg(s, a->rd, t32);
+ write_fp_sreg_merging(s, a->rd, a->rd, t32);
break;
case MO_16:
t32 =3D read_fp_hreg(s, a->rn);
f->gen_h(t32, t32, fpst);
- write_fp_sreg(s, a->rd, t32);
+ write_fp_hreg_merging(s, a->rd, a->rd, t32);
break;
default:
g_assert_not_reached();
@@ -8651,7 +8651,7 @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *=
a)
TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR_A64);
=20
gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
- write_fp_dreg(s, a->rd, tcg_rd);
+ write_fp_dreg_merging(s, a->rd, a->rd, tcg_rd);
}
return true;
}
@@ -8664,8 +8664,8 @@ static bool trans_FCVT_s_hs(DisasContext *s, arg_rr *=
a)
TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR_A64);
=20
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
- /* write_fp_sreg is OK here because top half of result is zero */
- write_fp_sreg(s, a->rd, tmp);
+ /* write_fp_hreg_merging is OK here because top half of result is =
zero */
+ write_fp_hreg_merging(s, a->rd, a->rd, tmp);
}
return true;
}
@@ -8678,7 +8678,7 @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *=
a)
TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR_A64);
=20
gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
- write_fp_sreg(s, a->rd, tcg_rd);
+ write_fp_sreg_merging(s, a->rd, a->rd, tcg_rd);
}
return true;
}
@@ -8692,8 +8692,8 @@ static bool trans_FCVT_s_hd(DisasContext *s, arg_rr *=
a)
TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR_A64);
=20
gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp);
- /* write_fp_sreg is OK here because top half of tcg_rd is zero */
- write_fp_sreg(s, a->rd, tcg_rd);
+ /* write_fp_hreg_merging is OK here because top half of tcg_rd is =
zero */
+ write_fp_hreg_merging(s, a->rd, a->rd, tcg_rd);
}
return true;
}
@@ -8707,7 +8707,7 @@ static bool trans_FCVT_s_sh(DisasContext *s, arg_rr *=
a)
TCGv_i32 tcg_ahp =3D get_ahp_flag();
=20
gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
- write_fp_sreg(s, a->rd, tcg_rd);
+ write_fp_sreg_merging(s, a->rd, a->rd, tcg_rd);
}
return true;
}
@@ -8721,7 +8721,7 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *=
a)
TCGv_i32 tcg_ahp =3D get_ahp_flag();
=20
gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
- write_fp_dreg(s, a->rd, tcg_rd);
+ write_fp_dreg_merging(s, a->rd, a->rd, tcg_rd);
}
return true;
}
@@ -8969,7 +8969,9 @@ static bool do_fcvt_f(DisasContext *s, arg_fcvt *a,
do_fcvt_scalar(s, a->esz | (is_signed ? MO_SIGN : 0),
a->esz, tcg_int, a->shift, a->rn, rmode);
=20
- clear_vec(s, a->rd);
+ if (!s->fpcr_nep) {
+ clear_vec(s, a->rd);
+ }
write_vec_element(s, tcg_int, a->rd, 0, a->esz);
return true;
}
--=20
2.34.1