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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH 20/76] fpu: Rename float_flag_output_denormal to
float_flag_output_denormal_flushed
Date: Fri, 24 Jan 2025 16:27:40 +0000
Message-Id: <20250124162836.2332150-21-peter.maydell@linaro.org>
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Our float_flag_output_denormal exception flag is set when
the fpu code flushes an output denormal to zero. Rename
it to float_flag_output_denormal_flushed:
* this keeps it parallel with the flag for flushing
input denormals, which we just renamed
* it makes it clearer that it doesn't mean "set when
the output is a denormal"
Commit created with
for f in `git grep -l float_flag_output_denormal`; do sed -i -e 's/float_f=
lag_output_denormal/float_flag_output_denormal_flushed/' $f; done
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/fpu/softfloat-types.h | 3 ++-
fpu/softfloat.c | 2 +-
target/arm/vfp_helper.c | 2 +-
target/i386/tcg/fpu_helper.c | 2 +-
target/m68k/fpu_helper.c | 2 +-
target/mips/tcg/msa_helper.c | 2 +-
target/rx/op_helper.c | 2 +-
target/tricore/fpu_helper.c | 6 +++---
fpu/softfloat-parts.c.inc | 2 +-
9 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 77bc172a074..4a806e3981a 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -156,7 +156,8 @@ enum {
float_flag_inexact =3D 0x0010,
/* We flushed an input denormal to 0 (because of flush_inputs_to_zero)=
*/
float_flag_input_denormal_flushed =3D 0x0020,
- float_flag_output_denormal =3D 0x0040,
+ /* We flushed an output denormal to 0 (because of flush_to_zero) */
+ float_flag_output_denormal_flushed =3D 0x0040,
float_flag_invalid_isi =3D 0x0080, /* inf - inf */
float_flag_invalid_imz =3D 0x0100, /* inf * 0 */
float_flag_invalid_idi =3D 0x0200, /* inf / inf */
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 648050be6fb..26f3a8dc87e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -5017,7 +5017,7 @@ floatx80 roundAndPackFloatx80(FloatX80RoundPrec round=
ingPrecision, bool zSign,
}
if ( zExp <=3D 0 ) {
if (status->flush_to_zero) {
- float_raise(float_flag_output_denormal, status);
+ float_raise(float_flag_output_denormal_flushed, status);
return packFloatx80(zSign, 0, 0);
}
isTiny =3D status->tininess_before_rounding
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 444702a4600..3c8f3e65887 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -47,7 +47,7 @@ static inline uint32_t vfp_exceptbits_from_host(int host_=
bits)
if (host_bits & float_flag_overflow) {
target_bits |=3D FPSR_OFC;
}
- if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal_flu=
shed)) {
target_bits |=3D FPSR_UFC;
}
if (host_bits & float_flag_inexact) {
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 7151e809643..de6d0b252ec 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -3271,7 +3271,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env)
(flags & float_flag_overflow ? FPUS_OE : 0) |
(flags & float_flag_underflow ? FPUS_UE : 0) |
(flags & float_flag_inexact ? FPUS_PE : 0) |
- (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE=
:
+ (flags & float_flag_output_denormal_flushed ? FPUS_UE |=
FPUS_PE :
0));
}
=20
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index e3f4a188501..339b73ad7dc 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -175,7 +175,7 @@ static int cpu_m68k_exceptbits_from_host(int host_bits)
if (host_bits & float_flag_overflow) {
target_bits |=3D 0x40;
}
- if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal_flu=
shed)) {
target_bits |=3D 0x20;
}
if (host_bits & float_flag_divbyzero) {
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index aeab6a1d8b3..ec38d9fde5e 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -6241,7 +6241,7 @@ static inline int update_msacsr(CPUMIPSState *env, in=
t action, int denormal)
}
=20
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
- if ((ieee_exception_flags & float_flag_output_denormal) &&
+ if ((ieee_exception_flags & float_flag_output_denormal_flushed) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0) {
mips_exception_flags |=3D FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) {
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 59dd1ae6128..b3ed822dd11 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -100,7 +100,7 @@ static void update_fpsw(CPURXState *env, float32 ret, u=
intptr_t retaddr)
SET_FPSW(X);
}
if ((xcpt & (float_flag_input_denormal_flushed
- | float_flag_output_denormal))
+ | float_flag_output_denormal_flushed))
&& !FIELD_EX32(env->fpsw, FPSW, DN)) {
env->fpsw =3D FIELD_DP32(env->fpsw, FPSW, CE, 1);
}
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 5d38aea143a..1b72dcc5f5c 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -43,7 +43,7 @@ static inline uint8_t f_get_excp_flags(CPUTriCoreState *e=
nv)
& (float_flag_invalid
| float_flag_overflow
| float_flag_underflow
- | float_flag_output_denormal
+ | float_flag_output_denormal_flushed
| float_flag_divbyzero
| float_flag_inexact);
}
@@ -99,7 +99,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint=
8_t flags)
some_excp =3D 1;
}
=20
- if (flags & float_flag_underflow || flags & float_flag_output_denormal=
) {
+ if (flags & float_flag_underflow || flags & float_flag_output_denormal=
_flushed) {
env->FPU_FU =3D 1 << 31;
some_excp =3D 1;
}
@@ -109,7 +109,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, ui=
nt8_t flags)
some_excp =3D 1;
}
=20
- if (flags & float_flag_inexact || flags & float_flag_output_denormal) {
+ if (flags & float_flag_inexact || flags & float_flag_output_denormal_f=
lushed) {
env->PSW |=3D 1 << 26;
some_excp =3D 1;
}
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index ec2467e9fff..73621f4a970 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -335,7 +335,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, floa=
t_status *s,
}
frac_shr(p, frac_shift);
} else if (s->flush_to_zero) {
- flags |=3D float_flag_output_denormal;
+ flags |=3D float_flag_output_denormal_flushed;
p->cls =3D float_class_zero;
exp =3D 0;
frac_clear(p);
--=20
2.34.1