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By doing an automated conversion of the whole file we avoid possibly using more than one fpst value in a set_rmode/op/restore_rmode sequence. Patch created with perl -p -i -e 's/FPST_FPCR(?!_)/FPST_FPCR_A32/g' target/arm/tcg/translate= -vfp.c Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-vfp.c | 54 +++++++++++++++++----------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 3cbe9a7418d..e1b8243c5d9 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -462,7 +462,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) if (sz =3D=3D 1) { fpst =3D fpstatus_ptr(FPST_FPCR_F16); } else { - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); } =20 tcg_rmode =3D gen_set_rmode(rounding, fpst); @@ -529,7 +529,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) if (sz =3D=3D 1) { fpst =3D fpstatus_ptr(FPST_FPCR_F16); } else { - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); } =20 tcg_shift =3D tcg_constant_i32(0); @@ -1398,7 +1398,7 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpS= PFn *fn, f0 =3D tcg_temp_new_i32(); f1 =3D tcg_temp_new_i32(); fd =3D tcg_temp_new_i32(); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); =20 vfp_load_reg32(f0, vn); vfp_load_reg32(f1, vm); @@ -1517,7 +1517,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, f0 =3D tcg_temp_new_i64(); f1 =3D tcg_temp_new_i64(); fd =3D tcg_temp_new_i64(); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); =20 vfp_load_reg64(f0, vn); vfp_load_reg64(f1, vm); @@ -2181,7 +2181,7 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_vfp_negs(vd, vd); } - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); vfp_store_reg32(vd, a->vd); return true; @@ -2246,7 +2246,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a= , bool neg_n, bool neg_d) /* VFNMA, VFNMS */ gen_vfp_negd(vd, vd); } - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); vfp_store_reg64(vd, a->vd); return true; @@ -2429,12 +2429,12 @@ static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) =20 static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) { - gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_FPCR)); + gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); } =20 static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) { - gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_FPCR)); + gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); } =20 DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith) @@ -2565,7 +2565,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_V= CVT_f32_f16 *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2599,7 +2599,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ @@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_V= CVT_b16_f32 *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); tmp =3D tcg_temp_new_i32(); =20 vfp_load_reg32(tmp, a->vm); @@ -2646,7 +2646,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_V= CVT_f16_f32 *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); =20 @@ -2680,7 +2680,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); @@ -2727,7 +2727,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRIN= TR_sp *a) =20 tmp =3D tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); gen_helper_rints(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2757,7 +2757,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) =20 tmp =3D tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); gen_helper_rintd(tmp, tmp, fpst); vfp_store_reg64(tmp, a->vd); return true; @@ -2803,7 +2803,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRIN= TZ_sp *a) =20 tmp =3D tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); tcg_rmode =3D gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rints(tmp, tmp, fpst); gen_restore_rmode(tcg_rmode, fpst); @@ -2836,7 +2836,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) =20 tmp =3D tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); tcg_rmode =3D gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rintd(tmp, tmp, fpst); gen_restore_rmode(tcg_rmode, fpst); @@ -2880,7 +2880,7 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRIN= TX_sp *a) =20 tmp =3D tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); gen_helper_rints_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); return true; @@ -2910,7 +2910,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) =20 tmp =3D tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); gen_helper_rintd_exact(tmp, tmp, fpst); vfp_store_reg64(tmp, a->vd); return true; @@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); vfp_load_reg32(vm, a->vm); - gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR)); + gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); vfp_store_reg64(vd, a->vd); return true; } @@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) vd =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); vfp_load_reg64(vm, a->vm); - gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR)); + gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR_A32)); vfp_store_reg32(vd, a->vd); return true; } @@ -3010,7 +3010,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VC= VT_int_sp *a) =20 vm =3D tcg_temp_new_i32(); vfp_load_reg32(vm, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); if (a->s) { /* i32 -> f32 */ gen_helper_vfp_sitos(vm, vm, fpst); @@ -3044,7 +3044,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); vfp_load_reg32(vm, a->vm); - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); if (a->s) { /* i32 -> f64 */ gen_helper_vfp_sitod(vd, vm, fpst); @@ -3161,7 +3161,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) vd =3D tcg_temp_new_i32(); vfp_load_reg32(vd, a->vd); =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); shift =3D tcg_constant_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -3223,7 +3223,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) vd =3D tcg_temp_new_i64(); vfp_load_reg64(vd, a->vd); =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); shift =3D tcg_constant_i32(frac_bits); =20 /* Switch on op:U:sx bits */ @@ -3307,7 +3307,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VC= VT_sp_int *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); vm =3D tcg_temp_new_i32(); vfp_load_reg32(vm, a->vm); =20 @@ -3347,7 +3347,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return true; } =20 - fpst =3D fpstatus_ptr(FPST_FPCR); + fpst =3D fpstatus_ptr(FPST_FPCR_A32); vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i32(); vfp_load_reg64(vm, a->vm); --=20 2.34.1