From nobody Sat Apr 5 17:48:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1737726064; cv=none; d=zohomail.com; s=zohoarc; b=C9Np0s1YoVmRKoDF8G1wpTNjfCYYyKNgvUcjGsda0MDJ/POWh740SPIFVNwUUTkIFrE9Tz9XrkZBWqew3KtamU6fcdkS2UZd5QizfYCYOmP7oienLGAr3QBYFbX2Vidwn/0MvPP9jJPgeq6XhQSAJFBfPQZK+/1qD01krXDAP7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1737726064; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MOJsvVT/dN9HRPSAhaVTAFQwWX2CVsbO5Ar7p91r8aU=; b=Hm0BgZ0TwE305hv5WIeRwQhzbI+7ZYJjXDfl3HurvONGwU/rjPELEy8/drI+clYMJovL46hecpGjgK2jE/qfo6/xOkztMi7mOnHhdLzC9EJEUrxHATdApA4pB9B2IyBd4/fzN6GkmVYiassUhqZZeVe0MJmSmyqkujnZ4XvpkDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173772606454216.367185215105792; Fri, 24 Jan 2025 05:41:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tbJvI-00025k-CF; Fri, 24 Jan 2025 08:40:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tbJu1-00073C-27 for qemu-devel@nongnu.org; Fri, 24 Jan 2025 08:39:25 -0500 Received: from mgamail.intel.com ([198.175.65.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tbJtz-00041c-CT for qemu-devel@nongnu.org; Fri, 24 Jan 2025 08:39:16 -0500 Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2025 05:39:00 -0800 Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa003.fm.intel.com with ESMTP; 24 Jan 2025 05:38:55 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737725956; x=1769261956; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AIvTamkBOmKspnXO3UXE/eRzJSG4/8lw/StlhSw6xEg=; b=lv/sKirUsCosB/4+OE8x9V7ObqpFW1atjIX/tlzHfallJENnbxUBTNR3 TSFmU2X6M/og87d2y7eFdtuxQj43AQ58cyA7PSIDY9o8Kjvui6LuGdLrU dAZz14qOZ1UBAdvCxYkP158BV003bahGaFP1dWR8xiTCaT4BuZxzuYha8 Dt8WdLnexb+2JpcvZBwhhn2z6j5ywzjQZp9hB/t3UtjB9+9tH/3lEPTBp 0gra1VLW6E5Fg1FVftYkZ28CBquuh6+vFG00dsSn5AAaFJRFeCDi6MW9u xy79/IN5Ng6qlZ8YPOXojbq9oEMKO/rosKzg5C8J6S/Dqoi1kZGqMJu+w g==; X-CSE-ConnectionGUID: txayt5SHQAmKcr/BAx79gQ== X-CSE-MsgGUID: /80qtJmJTRSHLsQ4KfAwWg== X-IronPort-AV: E=McAfee;i="6700,10204,11325"; a="49246483" X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="49246483" X-CSE-ConnectionGUID: WmHn80zLQV22oN/URjP/rQ== X-CSE-MsgGUID: 4GbByw3iST+eUc/xzSjrRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="111804389" From: Xiaoyao Li To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov Cc: Zhao Liu , "Michael S. Tsirkin" , Eric Blake , Markus Armbruster , Peter Maydell , Marcelo Tosatti , Huacai Chen , Rick Edgecombe , Francesco Lavra , xiaoyao.li@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 31/52] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f Date: Fri, 24 Jan 2025 08:20:27 -0500 Message-Id: <20250124132048.3229049-32-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250124132048.3229049-1-xiaoyao.li@intel.com> References: <20250124132048.3229049-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.13; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -63 X-Spam_score: -6.4 X-Spam_bar: ------ X-Spam_report: (-6.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1737726066534019100 Content-Type: text/plain; charset="utf-8" Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e., when topology level that cannot be enumerated by leaf 0xB, e.g., die or module level, are configured for the guest, e.g., -smp xx,dies=3D2. However, TDX architecture forces to require CPUID 0x1f to configure CPU topology. Introduce a bool flag, enable_cpuid_0x1f, in CPU for the case that requires CPUID leaf 0x1f to be exposed to guest. Introduce a new function x86_has_cpuid_0x1f(), which is the warpper of cpu->enable_cpuid_0x1f and x86_has_extended_topo() to check if it needs to enable cpuid leaf 0x1f for the guest. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 2 +- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a369cf90f5f6..4088bf63c48f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6725,7 +6725,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x1F: /* V2 Extended Topology Enumeration Leaf */ - if (!x86_has_extended_topo(env->avail_cpu_topo)) { + if (!x86_has_cpuid_0x1f(cpu)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } @@ -7588,7 +7588,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) * cpu->vendor_cpuid_only has been unset for compatibility with ol= der * machine types. */ - if (x86_has_extended_topo(env->avail_cpu_topo) && + if (x86_has_cpuid_0x1f(cpu) && (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b26e25ba15e0..ca6295605985 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2191,6 +2191,9 @@ struct ArchCPU { /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb; =20 + /* Force to enable cpuid 0x1f */ + bool enable_cpuid_0x1f; + /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; =20 @@ -2453,6 +2456,12 @@ void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); bool cpu_has_x2apic_feature(CPUX86State *env); =20 +static inline bool x86_has_cpuid_0x1f(X86CPU *cpu) +{ + return cpu->enable_cpuid_0x1f || + x86_has_extended_topo(cpu->env.avail_cpu_topo); +} + /* helper.c */ void x86_cpu_set_a20(X86CPU *cpu, int a20_state); void cpu_sync_avx_hflag(CPUX86State *env); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a76f34537908..741b50181ed9 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1871,7 +1871,7 @@ uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct= kvm_cpuid_entry2 *entries, break; } case 0x1f: - if (!x86_has_extended_topo(env->avail_cpu_topo)) { + if (!x86_has_cpuid_0x1f(env_archcpu(env))) { cpuid_i--; break; } --=20 2.34.1